A conductive adhesive composition, the composition containing: (A) conductive particles; (B) a thermosetting resin; and (C) a flux activator. The conductive particles contain a metal having a melting point of 200° C. or lower. In a volume-based cumulative particle size distribution of the conductive particles, a cumulative 50% particle diameter D50 is 3 to 10 μm, and a cumulative 10% particle diameter D10 is 2.4 μm or more. The flux activator contains a compound having a hydroxyl group and a carboxyl group.

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

An image sensor package includes: a package base substrate having a cavity extending inwards from an upper surface thereof, and including a plurality of upper surface connection pads and a plurality of lower surface connection pads; an image sensor chip in the cavity, and including a chip body having a first surface and a second surface facing each other, a sensor unit located in the first surface of the chip body, and a plurality of chip pads around the sensor unit; a filter glass above the image sensor chip, and including a transparent substrate and a plurality of redistribution patterns on a lower surface of the transparent substrate; and a plurality of connection terminals between the plurality of redistribution patterns and the plurality of chip pads and between the plurality of redistribution patterns and the plurality of upper surface connection pads.

Improving motion sensor robustness utilizing a room-temperature-volcanizing (RTV) material via a solder resist dam is presented herein. A sensor package comprises: a first semiconductor die; a second semiconductor die that is attached to the first semiconductor die to form a monolithic die; and a substrate comprising a top portion and a bottom portion, in which the top portion comprises a plurality of solder resist dams, the monolithic die is attached to the top portion of the substrate via the RTV material being disposed in a defined area of the top portion of the substrate, and the bottom portion of the substrate comprises electrical terminals that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board.

A semiconductor package includes spread inhibiting structure to constrain the movement of viscous material during fabrication. In some embodiments, the spread inhibiting structure comprises a recess in an underside of a package lid overlying the die. According to other embodiments, the spread inhibiting structure comprises polymer disposed on the lid underside proximate to a side of the packaged die. According to still other embodiments, the spread inhibiting structure comprises a polymer disposed around the top of the die to serve as a dam and contain spreading. In some embodiments, the viscous material may be a Thermal Integration Material (TIM) in an uncured state, and the polymer may be the TIM in a cured state.

A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.

A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y≤11 mass %, x+14y≤42 mass %, and x≥5.1 mass %.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

An anisotropic conductive film includes conductive particles disposed in an insulating resin layer. Zigzag arrangements are arranged at a predetermined pitch in an x direction on an xy plane in a plan view of the anisotropic conductive film with positions thereof in a y direction being periodically altered. The zigzag arrangements each include an arrangement Rb and an arrangement Rc repeatedly provided at predetermined intervals in the y direction. The arrangement Rb includes the conductive particles arranged at a positive inclination, and the arrangement Rc includes the conductive particles arranged at a negative inclination. This configuration can form a pseudo random regular disposition.

Provided is an electric circuit body including: a power semiconductor element; a first conductor plate configured to be connected to one surface of the power semiconductor element; a first sheet-shaped member having a first resin insulation layer and configured to at least cover a surface of the first conductor plate; a sealing material configured to seal each of the power semiconductor element, the first conductor plate, and an end of the first sheet-shaped member; and a first cooling member configured to be adhesively attached to the first sheet-shaped member. In the electric circuit body, the first sheet-shaped member includes : an embedded portion where the end of the first sheet-shaped member is covered with the sealing material; a heat dissipation surface as a region to overlap the surface of the first conductor plate; and a margin as a region between the embedded portion and the heat dissipation surface, the margin is located more inward than the heat dissipation surface, and the embedded portion is located more inward than the margin.