A power semiconductor device includes first and second disc-shaped electrodes and a wafer sandwiched between the electrodes. An outer insulating ring is attached to the first and second electrodes and surrounds the wafer. An inner insulating ring is located inside of the outer insulating ring and surrounds the wafer and a ring-shaped first flange portion laterally surrounds a main portion of the first electrode. An O-ring radially surrounds the main portion of the first electrode and is sandwiched in a vertical direction between the inner insulating ring and the first flange portion. In a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

A display apparatus including a circuit board, at least one LED stack configured to emit light, electrode pads disposed on the at least one LED stack and electrically connected to the at least one LED stack, and electrodes disposed on the electrode pads and electrically connected to the electrode pads, respectively, in which each of the electrodes has a fixed portion that is fixed to one of the electrode pads and an extending portion that is spaced apart from the one of the electrode pads, and the electrodes include at least two metal layers having different thermal expansion coefficients from each other.

The present application discloses a semiconductor device with an interface structure and a method for fabricating the interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.

A display device includes: a circuit substrate including a plurality of pixel circuit units and a plurality of pads on a first surface thereof, the plurality of pads being electrically connected to the pixel circuit units; a display substrate on the circuit substrate and including a plurality of light emitting elements electrically connected to the pixel circuit units; a circuit board on the circuit substrate and including a plurality of circuit board pads electrically connected to the pads; a heat dissipation substrate on a second surface of the circuit substrate, the second surface being opposite to the first surface; and a cover substrate on the heat dissipation substrate and partially overlapping the circuit substrate and the circuit board. Each of the plurality of pads is in direct contact with at least one of the plurality of circuit board pads.

A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.

Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

An integrated circuit package includes a lead frame, a first die adhered to the lead frame on a first side of the first die, and a first clip having a clip foot adhered to the lead frame. The first clip has a first side and a second side. A first die attachment region is defined by a first group of four notches in the first side of the first clip. The first clip extends from the lead frame and contacts a second side of the first die at the first die attachment region via a first layer of solder paste. The integrated circuit package further has a second die adhered to the second side of the first clip on a first side of the second die, and a second clip having a clip foot adhered to the lead frame. The second clip has a first side and a second side. A second die attachment region is defined by a second group of four notches in the first side of the second clip. The second clip extends from the lead frame and contacts a second side of the second die at the second die attachment region via a second layer of solder paste.