Power Semiconductor Device

Abstract

A power semiconductor device includes first and second disc-shaped electrodes and a wafer sandwiched between the electrodes. An outer insulating ring is attached to the first and second electrodes and surrounds the wafer. An inner insulating ring is located inside of the outer insulating ring and surrounds the wafer and a ring-shaped first flange portion laterally surrounds a main portion of the first electrode. An O-ring radially surrounds the main portion of the first electrode and is sandwiched in a vertical direction between the inner insulating ring and the first flange portion. In a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

Claims

1-16. (canceled)

17. A power semiconductor device comprising: a disc-shaped first electrode having a first contact face; a disc-shaped second electrode having a second contact face opposite to the first contact face; a wafer sandwiched between the first electrode and the second electrode; an outer insulating ring attached to the first electrode and to the second electrode, the outer insulating ring surrounding the wafer; an inner insulating ring inside of the outer insulating ring and surrounding the wafer; a ring-shaped first flange portion laterally surrounding a main portion of the first electrode; and an O-ring radially surrounding the main portion of the first electrode and being sandwiched in a vertical direction perpendicular to the first contact face between the inner insulating ring and the first flange portion, wherein the O-ring is resiliently reversibly deformable and wherein in a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

18. The power semiconductor device of claim 17, wherein the inner insulating ring comprises polymer material.

19. The power semiconductor device of claim 17, wherein the outer insulating ring comprises ceramic material.

20. The power semiconductor device of claim 17, wherein the first electrode or the second electrode are made from copper.

21. The power semiconductor device of claim 17, wherein the first flange portion comprises steel.

22. The power semiconductor device of claim 17, wherein a first portion of the first flange portion is fully overlapped with a second portion of the inner insulating ring in a view along the radial direction and wherein the O-ring is arranged radially outside of the first portion and of the second portion.

23. The power semiconductor device of claim 17, further comprising an exchangeable copper insert arranged between the first electrode and the wafer.

24. The power semiconductor device of claim 17, wherein the inner insulating ring has a first end and a second end in the vertical direction, wherein the O-ring is arranged on the first end and wherein the second end has a radially protruding bottom portion extending radially inwards to the second electrode.

25. The power semiconductor device of claim 24, further comprising a rubber protection ring attached to the wafer surrounding the wafer radially inside of the inner insulating ring, wherein the bottom portion contacts the rubber protection ring.

26. The power semiconductor device of claim 25, wherein a space is defined by the inner insulating ring, the first electrode, the rubber protection ring and the first flange portion.

27. The power semiconductor device of claim 17, wherein the cross-section of the O-ring has an oval shape.

28. A power semiconductor device comprising: a disc-shaped first electrode having a first contact face; a disc-shaped second electrode having a second contact face opposite to the first contact face; a wafer sandwiched between the first electrode and the second electrode; an outer insulating ring attached to the first electrode and to the second electrode, the outer insulating ring surrounding the wafer; an inner insulating ring inside of the outer insulating ring and surrounding the wafer; a ring-shaped first flange portion laterally surrounding a main portion of the first electrode; and an O-ring radially surrounding the main portion of the first electrode and being sandwiched in a vertical direction perpendicular to the first contact face between the inner insulating ring and the first flange portion; wherein the first electrode has a second flange portion radially extending from the main portion of the first electrode on a side of the first flange portion opposite to the O-ring; and wherein the O-ring is resiliently reversibly deformable and wherein in a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

29. The power semiconductor device of claim 28, wherein the second flange portion comprises copper.

30. The power semiconductor device of claim 28, wherein in an orthogonal projection onto a plane parallel to the first contact face, the first flange portion overlaps the second flange portion in an area radially extending between the O-ring and the main portion of the first electrode.

31. The power semiconductor device of claim 28, wherein the first flange portion has a first flat surface portion and the second flange portion has a second flat surface portion that is parallel to the first flat surface portion and that is pressed onto the first flat surface portion.

32. The power semiconductor device of claim 31, wherein in an orthogonal projection onto a plane parallel to the first contact face, the first flat surface portion and the second flat surface portion extend in an area between the O-ring and the main portion of the first electrode.

33. The power semiconductor device of claim 31, further comprising a polymer foil sandwiched between the first flat surface portion and the second flat surface portion.

34. A power semiconductor device comprising: a first copper electrode having a first contact face and being disc-shaped; a second copper electrode having a second contact face and being disc-shaped, the second contact face being opposite to the first contact face; a wafer sandwiched between the first electrode and the second electrode; a ceramic outer insulating ring attached to the first electrode and to the second electrode, the outer insulating ring surrounding the wafer; a polymer inner insulating ring inside of the outer insulating ring and surrounding the wafer, the inner insulating ring comprising polymer material; a ring-shaped first flange portion laterally surrounding a main portion of the first electrode; and an O-ring radially surrounding the main portion of the first electrode and being sandwiched in a vertical direction perpendicular to the first contact face between the inner insulating ring and the first flange portion, wherein the O-ring is resiliently reversibly deformable and wherein in a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

35. The power semiconductor device of claim 34, wherein a first portion of the first flange portion is fully overlapped with a second portion of the inner insulating ring in a view along the radial direction and wherein the O-ring is arranged radially outside of the first portion and of the second portion.

36. The power semiconductor device of claim 34, wherein the inner insulating ring has a first end and a second end in the vertical direction, wherein the O-ring is arranged on the first end and wherein the second end has a radially protruding bottom portion extending radially inwards to the second electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Detailed embodiments of the invention will be explained below with reference to the accompanying figures, in which:

[0017] FIG. 1 shows a partial cross-sectional view of a power semiconductor device according to an embodiment;

[0018] FIG. 2 shows a vertical cross-section of the power semiconductor device of FIG. 1;

[0019] FIG. 3 shows a vertical cross-section of a first electrode included in the power semiconductor device of FIG. 1;

[0020] FIG. 4 shows a vertical cross-section of an O-ring included in the power semiconductor device of FIG. 1;

[0021] FIG. 5 shows a cross-section of a second electrode included in the power semiconductor device of FIG. 1;

[0022] FIG. 6a to 6c show respectively a portion of the vertical cross-section of FIG. 2 for different assembling heights;

[0023] FIG. 7 shows a vertical cross-section of a first modified embodiment of the power semiconductor of FIG. 1; and

[0024] FIG. 8 shows a partial cross-sectional view of a second modified embodiment of the power semiconductor device.

[0025] The reference signs used in the figures and their meanings are summarized in the list of reference signs. Generally, similar elements have the same reference signs throughout the specification. The described embodiments are meant as examples and shall not limit the scope of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0026] A first embodiment power semiconductor device will first be described along with variations. Particular examples will then be provided with respect to the drawings.

[0027] In this embodiment, a power semiconductor device comprises a disc-shaped first electrode 12a having a first contact face 14a and a disc-shaped second electrode 12b having a second contact face 14b opposite to the first contact face 14a. A wafer 16 is sandwiched between the first electrode 12a and the second electrode 12b. An outer insulating ring 24 is attached to the first electrode 12a and to the second electrode 12b. The outer insulating ring 24 surrounds the wafer 16. An inner insulating ring 42; 42′ is located inside of the outer insulating ring 24 and surrounds the wafer 16. A ring-shaped first flange portion 50 laterally surrounding a main portion 121a of the first electrode 12a, a radial first direction R being parallel to the first contact face 14a.

[0028] An O-ring 20 radially surrounds the main portion 121a of the first electrode 12a and is sandwiched in a second direction Z perpendicular to the first contact face 14a between the inner insulating ring 42; 42′ and the first flange portion 50. In a relaxed state, the O-ring 20 has a cross-section that is elongated in a vertical direction Z perpendicular to the radial direction R such that in a relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in the radial direction. The O-ring 20 is resiliently reversibly deformable.

[0029] For example, the O-ring has an oval shape in cross-section, wherein the oval cross-section is elongated in a direction perpendicular to the first contact face. Therein the cross-section is taken along a plane orthogonal to a main axis of the O-ring, i.e. along a plane orthogonal to the first contact face and parallel to the radial direction, which is parallel to the first contact face. The cross-section of the O-ring is formed, shaped and/or designed such that the O-ring is capable of providing a relatively high reactive force for different compression states of the O-ring. The O-ring is made out of an elastic and/or resilient material. The O-ring is elastic. The O-ring is resilient. The O-ring is reversibly deformable. The O-ring comprises a cross-section and is made out of a material such that the O-ring deforms when an external force is applied to the O-ring, in particular along the vertical direction. The O-ring returns to its original size and shape when that force is removed.

[0030] In various embodiments, the oval shape of the O-ring allows to provide a relatively high reactive force for a variety of different assembly heights when using the same housing for semiconductor wafers having different wafer thicknesses. That means that the oval shaped O-ring can provide a relatively high reactive force for different compression states of the O-ring.

[0031] In an exemplary embodiment, the inner insulating ring is made of a polymer material. Polymer material has properties that are especially appropriate for the inner insulating ring to protect the outer insulating ring in case of electrical arcing to prevent explosion of the housing.

[0032] In an exemplary embodiment, the outer insulating ring is made of ceramic material. Ceramic material has ideal electrically insulating properties.

[0033] In an exemplary embodiment, the first electrode and/or the second electrode are made from copper. Copper has a very high electrical conductivity and is therefore most appropriate as a material for the first and the second electrode.

[0034] In an exemplary embodiment, the first flange portion is made of steel. Steel can withstand high temperatures and is therefore especially resistant to the are plasma in case of arcing.

[0035] In an exemplary embodiment, the first electrode has a second flange portion radially extending from a main portion of the first electrode on a side of the first flange portion opposite to the O-ring. The second flange portion, which may be an integral part of the first electrode, facilitates to form a gas-tight housing.

[0036] In an exemplary embodiment, the second flange portion is made from copper. In such exemplary embodiment, a first flange portion made of steel might provide a most efficient protection of the second flange portion against are plasma in case of electrical arcing.

[0037] In an exemplary embodiment, in an orthogonal projection onto a plane parallel to the first contact face, the first flange portion overlaps the second flange portion in an area radially extending between the O-ring and the main portion of the first electrode. In such arrangement the second flange portion can be protected against are plasma most efficiently by the first flange portion in case of electrical arcing.

[0038] In an exemplary embodiment, the first flange portion has a first flat surface portion and the second flange portion has a second flat surface portion which is parallel to the first flat surface portion and which is pressed onto the first flat surface portion, wherein, in an orthogonal projection onto a plane parallel to the first contact face, the first flat surface portion and the second flat surface portion extend in an area between the O-ring and the first electrode. The first flat surface portion being pressed against the second flat surface portion allows to minimize the gap between the first flange portion and the second flange portion so that the first flange portion can protect the second flange portion most efficiently against arc-plasma in case of electrical arcing.

[0039] In an exemplary embodiment, a polymer foil is sandwiched between the first flat surface portion and the second flat surface portion. The polymer foil in this exemplary embodiment provides an efficient sealing so that the are plasma cannot enter in a gap between the first and the second flange portion.

[0040] In an exemplary embodiment, a first portion of the first flange portion is fully overlapped with a second portion of the inner insulating ring in a view along the radial direction, wherein the O-ring is arranged radially outside of the first portion and of the second portion. The overlapping first and second portion can effectively shield the O-ring from any arc-plasma in case of electrical arcing.

[0041] In an exemplary embodiment, the power semiconductor device comprises an exchangeable copper insert between the first electrode and the wafer. The exchangeable copper insert allows to use the same housing parts for different wafer diameters. In such case, only the exchangeable copper insert has to be adapted to the corresponding wafer diameter, whereas the remaining housing parts can be used for a variety of different wafer diameters. Throughout this specification, an element being exchangeable means that this element is a separate part, i.e., not integral with other parts of the power semiconductor device (but may be connected detachably to other parts).

[0042] In an exemplary embodiment, the inner insulating ring has a first end and a second end in the direction perpendicular to the radial direction, wherein the O-ring is arranged on the first end and wherein the second end has a radially protruding bottom portion extending radially inwards to the second electrode. In such exemplary embodiment the bottom portion of the inner insulating ring can efficiently shield any part of the housing provided below the bottom portion against arc-plasma in case of electrical arcing. In this exemplary embodiment a rubber protection ring may be attached to and surround the wafer radially inside of the inner insulating ring, wherein the bottom portion may contact the rubber protection ring. The direct contact between the bottom portion and the rubber protection ring can efficiently seal a space above the bottom portion.

[0043] In an exemplary embodiment, a space is defined by the inner insulating ring, the first electrode, the rubber protection ring and the first flange portion. Such space provides space for the arc-plasma in case of a device failure to thereby reduce the risk of an explosion because the space can relieve the pressure increase in case of electrical arcing.

[0044] Referring now to the figures, FIG. 1 shows a partial cross-sectional view of a power semiconductor device 10 according to an embodiment of the invention, and FIG. 2 shows a vertical cross-section of the power semiconductor device 10 shown in FIG. 1. The power semiconductor device 10 comprises a disc-shaped first electrode 12a, a disc-shaped second electrode 12b, a wafer 16 sandwiched between the first electrode 12a and the second electrode 12b, an outer insulating ring 24, an inner insulating ring 42, a ring-shaped first flange portion 50, and an O-ring 20.

[0045] In addition, a molybdenum layer 70 may be arranged between the wafer 16 and the second electrode 12b as a thermal buffer layer. The wafer 16 may be bonded to the molybdenum layer 70, for example by a low temperature bonding process (LTB). Alternatively, the first molybdenum 70 may be free-floating without being bonded to the wafer 16.

[0046] The wafer 16 may be a silicon wafer, for example. A switch such as a thyristor, a transistor or a power diode may be implemented in the wafer 16.

[0047] The first electrode 12a has a first contact face 14a and the second electrode 12b has a second contact face 14b opposite to the first contact face 14a. Therein, the first contact face 14a and the second contact face 14b are both flat and parallel to each other. Exemplarily, the first contact face 14a and the second contact face 14b may have a circular shape as shown in FIG. 1. When the power semiconductor device 10 is stacked with other equally designed press-pack power semiconductor devices 10 in a stack, the first electrode 12a and the second electrode 12b may act as contact pole pieces.

[0048] The outer insulating ring 24 has the form of a hollow cylinder and may further comprise a fin structure as shown in FIGS. 1 and 2 to ensure the necessary clearance and/or creepage distances between the first electrode 12a and the second electrode 12b. As shown in FIG. 2, the outer insulating ring 24 has an upper first end and a lower second end. Throughout the specification, an upper side of the power semiconductor device 10 is a side of the power semiconductor device 10 where the first contact face 14a is arranged and a lower side of the power semiconductor device 10 is a side of the power semiconductor device 10 where the second contact face 14b is arranged. It is attached with its first end to the first electrode 12a and with its second end to the second electrode 12b. The inner insulating ring 42 is laterally arranged inside of the outer insulating ring 24, i.e. the outer insulating ring 24 radially surrounds the inner insulating ring 42, wherein a radial direction R is a direction that is parallel to the first contact face 14a and that extends away from a lateral center of the first contact face 14a. Both, the outer insulating ring 24 and the inner insulating ring 42 are arranged to radially surround the wafer 16. The outer insulating ring 24 forms a side wall of a hermetically sealed housing of the power semiconductor device 10.

[0049] FIG. 3 shows a vertical cross-section of the first electrode 12a. As indicated in FIG. 3, the first electrode 12a has a main portion 121a and a second flange portion 52 radially extending from an upper end of the main portion 121a. The upper end of the first electrode 12a is that end of the first electrode 12a which is in the vertical direction Z at a side where the first contact face 14a is arranged. On its lower side 18 the first electrode 12a has a recess 15 for receiving a later described spring element 80. As can be seen from FIGS. 1 to 3, the first flange portion 50 radially surrounds the main portion 121a of the first electrode 12a.

[0050] In the power semiconductor device 10 as shown in FIGS. 1 and 2, the O-ring 20 radially surrounding the main portion 121a of the first electrode 12a is sandwiched between an upper end of the inner insulating ring 42 and a lower side of the first flange portion 50. FIG. 4 shows a vertical cross-section of the O-ring 20 in a relaxed state, i.e. when no pressure is applied to the O-ring 20 by the inner insulating ring 42 and the first flange portion 50. In the relaxed state, the O-ring 20 has a cross-section along a plane parallel to the radial direction R and a vertical direction Z perpendicular to the first contact face 14a, which plane is the drawing plane of FIG. 4.

[0051] The cross-section shown in FIG. 4 is orthogonal to a main axis of the O-ring 20. Therein, the cross-section is elongated in the vertical direction Z perpendicular to the radial direction R. Along the vertical direction Z, the O-ring 20 has a first width d1 and along the radial direction R the O-ring 20 has a second width d2, which is smaller than the first width d1. Exemplarily, the first width d1 is the largest width of the O-ring 20 in the vertical cross-section and the second width d2 is the smallest width of the O-ring 20 in the vertical cross-section. Exemplarily, the O-ring 20 has a cross-section shape that is oval, as shown in the figures. Exemplarily, the O-ring 20 is made of silicone material. The silicone material has good elastic properties and has a sufficient heat resistance to withstand the thermal load during operation of the power semiconductor device. Exemplarily, the O-ring 20 is made of another resiliently and/or reversibly deformable material.

[0052] The inner insulating ring 42 may be made of a polymer material which has good electrical insulating properties. The outer insulating ring 24 may be made of a ceramic material. The inner insulating ring 42 can efficiently shield the outer insulating ring 24 against the are plasma in case of electrical arcing and prevent explosion of the housing of the power semiconductor device 10 in case of a device failure and electrical arcing.

[0053] In the power semiconductor device 10 shown in FIGS. 1 and 2, the second flange portion 52 is arranged and radially extends on a side of the first flange portion 50 opposite to the O-ring 20. The first electrode 12a and the second electrode 12b is made from a material having high electrical conductivity such as copper. In particular the second flange portion 52 may be made from copper which is a relatively soft material that may easily be damaged when getting into contact with an arc plasma in case of electrical arcing due to a device failure.

[0054] The first flange portion 50 is made of a material that can withstand high temperatures of an arc plasma in case of electrical arcing. Exemplarily it may be made of steel. In an orthogonal projection onto a plane parallel to the first contact face 14a, the first flange portion 50 overlaps the second flange portion 52 in an area radially extending between the O-ring 20 and the main portion 121a of the first electrode 12a. The first flange portion 50 has a first flat surface portion 50a and the second flange portion 52 has a second flat surface portion 52a which is parallel to the first flat surface portion 50a and which is pressed onto the first flat surface portion 50a, wherein in an orthogonal projection onto a plane parallel to the first contact face 14a, the first flat surface portion 50a and the second flat surface portion 52a extend in an area between the O-ring 20 and the first electrode 12a.

[0055] In the exemplary embodiment shown in FIG. 1, the first flat surface portion 50a is shown to be in direct contact with the second flat surface portion 52a. In an first modified embodiment as shown in FIG. 7, a polymer foil 56 may be sandwiched between the first flat surface portion 50a and the second flat surface portion 52a to provide an additional sealing effect. The polymer foil 56 may be a Polytetrafluoroethylene (PTFE) foil. It may exemplarily have a thickness in a range between 50 μm and 500 μm. Besides the additional feature of the polymer foil 56 the first modified embodiment may be identical to the embodiment illustrated in FIGS. 1 and 2.

[0056] As can be seen in FIGS. 1 and 2 a first portion 50b of the first flange portion 50 is fully overlapped with a second portion 42b of the inner insulating ring 42 in a view along the radial direction R. The O-ring 20 is arranged radially outside of the first portion 50b and of the second portion. With the radial overlap of the first portion 50b and the second portion 42b the O-ring 20 is shielded against an arc plasma generated in the power semiconductor device 10 in case of electrical arcing due to a device failure.

[0057] The inner insulating ring 42 has a first end and a second end in the vertical direction Z perpendicular to the radial direction R, wherein the O-ring 20 is arranged on the first end. The second end has a radially protruding bottom portion 42a extending radially inwards to the second electrode 12b. A rubber protection ring 38 is attached to and surrounds the wafer 16 radially inside of the inner insulating ring 42. The bottom portion 42a contacts the rubber protection ring 38 so that a space 60 is defined by the inner insulating ring 42, the first electrode 12a, the rubber protection ring 38 and the first flange portion 50. The space may exemplarily be filled with a protection gas such as nitrogen or helium. In case of electrical arcing due to a device failure a pressure increase in the housing of the power semiconductor device 10 can be kept at a relatively low level and thereby explosion of the housing can be prevented by providing the space 60.

[0058] The power semiconductor device 10 comprises an exchangeable copper insert 85 between the first electrode 12a and the wafer 16. With such exchangeable copper insert 85 the electrical contact area between first electrode 12a and a main contact on the wafer 16 can be adjusted for different wafer diameters. Accordingly, it is possible to use the same housing (including the first electrode 12a, the second electrode 12b, the outer insulating ring 24, the first flange portion 50 and the inner insulating ring 42) also for various chip diameters by respectively using different sized copper inserts.

[0059] In the exemplary embodiment shown in FIG. 1, a gate lead 90 is guided through a first radial opening 92 in the inner insulating ring 42 and through a second radial opening 94 in the outer insulating ring 24. The gate lead 90 is further guided through a channel in the copper insert 85 or in the first electrode 12a or between the copper insert 85 and the first electrode 12a to a control terminal at the lateral center of the wafer 16. The copper insert 85 has an opening which is aligned with the above mentioned recess 15 in the first gate electrode 12a for receiving a spring element 80 used for pressing the gate lead 90 or a gate contact connected to the gate lead 90 onto the control terminal of the wafer 16.

[0060] FIG. 5 shows a vertical cross-section of the second electrode 12b included in the power semiconductor device of FIG. 1. It comprises a main portion 121b and a third flange portion 54 which is radially extending from a lower side of the main portion 121b. The lower side of the main portion 121b forms the second contact face 14b and an upper side 17 of the main portion 121b is electrically connected to the molybdenum layer 70. The second electrode 12b is attached to the outer insulating ring 24 with the third flange portion 54.

[0061] FIGS. 6a to 6c show respectively a portion of the vertical cross-section of FIG. 2 for different assembling heights due to different wafer thicknesses. The different assembling heights result in different compression states of the O-ring 20. In FIG. 6a the O-ring 20 is vertically compressed to a vertical width h1 (relatively low compression state), in FIG. 6b the O-ring 20 is compressed to a vertical width h2<h1 (medium compressed state), and in FIG. 6c the O-ring is compressed to a vertical width h3<h2 (strongly compressed state). Due to the cross-section of the O-ring 20 which is elongated in the vertical direction, such as the oval shape of the vertical cross-section of the O-ring 20 exemplarily shown in the figures, the reactive force of the O-ring 20 is relatively high for all three different compression states and a good sealing effect between the first flange portion 50 and the inner insulating ring 42 can be achieved for different assembling heights due to different wafer thicknesses.

[0062] It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the scope of the invention as defined by the appended claims.

[0063] For example, FIG. 8 shows a partial cross-sectional view of a power semiconductor device 10′ which is a second modified embodiment of the power semiconductor device 10. The power semiconductor device 10′ differs from the power semiconductor device 10 of FIG. 1 only in that the bottom portion 42a′ of an inner insulating ring 42′ extending radially inwards to the second electrode 12b has a different shape than the bottom portion of inner insulating ring 42. Specifically, the bottom portion 42′ has a step-like shape in a vertical cross-section.

[0064] In the embodiment as shown in FIG. 1, the rubber protection ring 38 covers only a side surface and part of a top surface of the wafer 16. However, the rubber protection ring 38 may also cover other parts of a wafer surface, e.g. a lower side of the wafer 16 or only part of the side surface.

[0065] In the above embodiments, the wafer 16 is described with a control terminal that is connected to the outside via a gate lead 90. However, the wafer 16 may have no control terminal and no gate lead 90 may be provided. Accordingly, the outer insulating ring 24 may have no first radial opening 92 and the inner insulating ring 42 may have no second radial opening 94.

[0066] A second molybdenum layer may be arranged as a thermal buffer layer between the wafer 16 and the first electrode 12a.

[0067] The power semiconductor device 10 was described with the exchangeable copper insert 85 arranged between the wafer 16 and the first electrode 12a. However, in another exemplary embodiment no copper insert 85 may be interposed between the first electrode 12a and the wafer 16.

[0068] It should be noted that the term “comprising” does not exclude other elements or steps and that the indefinite article “a” or “an” does not exclude the plural. Also elements described in association with different embodiments may be combined.