Patent classifications
H01L24/76
Extrusion-based additive manufacturing system for 3D structural electronic, electromagnetic and electromechanical components/devices
The present invention provides a system and method for making a three-dimensional electronic, electromagnetic or electromechanical component/device by: (1) creating one or more layers of a three-dimensional substrate by depositing a substrate material in a layer-by-layer fashion, wherein the substrate includes a plurality of interconnection cavities and component cavities; (2) filling the interconnection cavities with a conductive material; and (3) placing one or more components in the component cavities.
PRECISION ALIGNMENT OF MULTI-CHIP HIGH DENSITY INTERCONNECTS
Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.
SCANNING ALIGNMENT DEVICE AND SCANNING METHOD THEREFOR
A scanning alignment apparatus and scanning methods thereof are disclosed. The scanning alignment apparatus is used to scan a substrate and includes a transflective lens unit, an imaging element unit, an alignment lens unit and an illumination lens unit. The alignment lens unit includes a plurality of sub-alignment lens units, and the imaging element unit includes a plurality of imaging elements. Each of the sub-alignment lens units corresponds to a respective one of the imaging elements. The scanning alignment apparatus and scanning methods provided in the present invention can achieve higher scanning efficiency and thus enhanced productivity and product throughput.
Semiconductor device processing method for material removal
A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.
Electrical interconnection of circuit elements on a substrate without prior patterning
A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.
PLATING INTERCONNECT FOR SILICON CHIP
A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
Plating interconnect for silicon chip
A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
AUTOMATIC REGISTRATION BETWEEN CIRCUIT DIES AND INTERCONNECTS
- Ankit Mahajan ,
- Mikhail L. Pekurovsky ,
- Matthew S. Stay ,
- Daniel J. Theis ,
- Ann M. Gillman ,
- Shawn C. Dodds ,
- Thomas J. Metzler ,
- Matthew R.D. Smith ,
- Roger W. Barton ,
- Joseph E. Hernandez ,
- Saagar A. Shah ,
- Kara A. Meyers ,
- James Zhu ,
- Teresa M. Goeddel ,
- Lyudmila A. Pekurovsky ,
- Jonathan W. Kemling ,
- Jeremy K. Larsen ,
- Jessica Chiu ,
- Kayla C. Niccum
Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed on a substrate with contact pads aligned with channels on the substrate. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward the contact pads to obtain the automatic registration.
PACKAGING SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed.
The mounting region includes a cavity portion formed by recessing a portion of the core substrate, a cavity portion side surface formed inside the core substrate in a thickness direction of the core substrate to form an outer periphery of the cavity portion, and a first heat dissipation portion disposed adjacent to the outer periphery of the cavity portion.
The first heat dissipation portion is a thermal path through which heat of the packaging substrate is transmitted to the outside.
The first heat dissipation portion includes one or more heat dissipation vias each having an area of 5,000 ?m.sup.2 to 75 mm.sup.2 when viewed from the upper surface of the packaging substrate.
The packaging substrate may effectively emit heat generated during an element driving process, and may have excellent long-term durability and reliability.
BARE DIE INTEGRATION WITH PRINTED COMPONENTS ON FLEXIBLE SUBSTRATE WITHOUT LASER CUT
Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.