Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

A heat conductive paste including silver fine particles having an average particle diameter of primary particles of 40 to 350 nm, a crystallite diameter of 20 to 70 nm, and a ratio of the average particle diameter to the crystallite diameter of 1 to 5, an aliphatic primary amine and a compound having at least one phosphoric acid group. The heat conductive paste includes 1 to 40 parts by mass of the aliphatic primary amine and 0.001 to 2 parts by mass of the compound having at least one phosphoric acid group based on 100 parts by mass of the silver fine particles. The heat conductive paste has a high conductivity.

A power module is provided. The power module includes a substrate, a power conversion chip that is disposed on the substrate and an insulating film that is formed on a structure in which the power conversion chip is disposed on the substrate. Additionally, the power module includes a metal mold that encases the structure that is coated with the insulating film. Additionally, the power module provides a simplified structure and improved heat dissipation performance compared to conventional power modules.

The present invention provides a silicone skeleton-containing polymer including a silicone skeleton shown by the following formula (1) and having a weight average molecular weight of 3,000 to 500,000.

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This can provide a silicone skeleton-containing polymer that can easily form a fine pattern with a large film thickness, and can form a cured material layer (cured film) that is excellent in various film properties such as crack resistance and adhesion properties to a substrate, electronic parts, and a semiconductor device, particularly a base material used for a circuit board, and has high reliability as a film to protect electric and electronic parts and a film for bonding substrates; and a photo-curable resin composition that contains the polymer, a photo-curable dry film thereof, a laminate using these materials, and a patterning process.

A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.