Patent classifications
H01L24/84
Semiconductor devices and methods of making the same
In one embodiment, methods for making semiconductor devices are disclosed.
Semiconductor device with metal film, power conversion device with the semiconductor device, and method of manufacturing the semiconductor device
A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.
Power semiconductor module for PCB embedding, power electronic assembly having a power module embedded in a PCB, and corresponding methods of production
A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.
Package including multiple semiconductor devices
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.
LOW STRESS ASYMMETRIC DUAL SIDE MODULE
Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
Cooling apparatus, semiconductor module, and vehicle
A semiconductor module including a cooling apparatus and a semiconductor device mounted on the cooling apparatus is provided. The cooling apparatus includes a cooling fin arranged below the semiconductor device, a main-body portion flow channel through which a coolant flows in a predetermined direction to cool the cooling fin, a first coolant flow channel that is connected to one side of the main-body portion flow channel and has a first inclined portion upwardly inclined toward the main-body portion flow channel, and a conveying channel that, when seen from above, lets the coolant into the first coolant flow channel from a direction perpendicular to the predetermined direction or lets the coolant out of the first coolant flow channel in the direction perpendicular to the predetermined direction.
Cascode semiconductor
This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.
High voltage semiconductor devices having improved electric field suppression
A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.
Compact low inductance chip-on-chip power card
Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame, a P lead frame, and an O lead frame each having a body portion and a terminal portion. The O lead frame is located between the N lead frame and the P lead frame. The power card includes a first power device located between the N lead frame and the O lead frame, with a first side coupled to the body portion of the N lead frame and a second side coupled to the body portion of the O lead frame. The power card includes a second power device located between the O lead frame and the P lead frame, with a first side coupled to the body portion of the O lead frame and a second side coupled to the body portion of the P lead frame.
Power Semiconductor Module with Laser-Welded Leadframe
A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.