A coupling element for providing external coupling to a semiconductor die within an integrated circuit package. The coupling element comprises a flexible laminate structure comprising a flexible, electrically insulating substrate layer, a first conductive layer bonded to a first surface of the substrate layer, and a second conductive layer bonded to a second surface of the substrate layer. The coupling element is arranged to be coupled to the semiconductor die such that the first and second conductive layers are electrically coupled to electrical contacts of the semiconductor die. The coupling element is further arranged to extend through the integrated circuit package when electrically coupled to the semiconductor die, and for the first and second conductive layers to be further electrically coupled to at least one external component.

A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

A method of manufacturing a semiconductor package according to the present inventive concepts comprises preparing a printed circuit board (PCB) including a protected layer, exposing a portion of the protected layer from the insulating layer, forming a solder ball land by processing the exposed surface of the protected layer, forming a solder ball on the solder ball land, and mounting a semiconductor chip on the solder ball formed on the PCB. The solder balls include copper of about 0.01 wt % to about 0.5 wt %.

A semiconductor device includes a leadframe that includes contact pins and a semiconductor die that has protruding connection formations. A flexible support member is disposed between the leadframe and the semiconductor die and supports the semiconductor die. The flexible support member has electrically conductive lines that extend between the leadframe and the semiconductor die. The electrically conductive lines of the flexible support member are electrically coupled with the contact pins of the leadframe and with the connection formations of the semiconductor die.

An apparatus including components to stack semiconductor device die.

The present invention relates to a method of manufacturing a carrier tape, wherein a TAB tape including a base film having a central area and edge areas at both directions of the central area, a wiring pattern formed at the central area of the base film, a transfer area formed at the edge area of the base film and exposed by the base film, a plurality of sprocket holes arranged in a row on the transfer area and a metal pattern discretely formed from the wiring pattern, and formed at the edge areas of the base film, wherein the metal pattern is formed with a paired structure formed at both sides of the plurality of sprocket holes, such that the present invention has an advantageous effect in that no Cu layer or a metal layer exists at a portion of the sprocket holes from which friction is generated by a driving roller during assembly work between a drive IC and chips/drive IC and panel to dispense with generation of foreign objects such as Cu particles, thereby enhancing reliability of the product.

Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the cutting portion within a resin application portion, the problem of occurrence of cracks along a width of a narrow wiring can be avoided. The tape may include a first lead and a second lead formed on a dielectric substrate and a cutting portion formed on one of the first lead and the second lead wherein the cutting portion is formed within a resin application portion.

A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.