An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface inclined at a first angle, and provided with light receiving surface electrodes on the light receiving surface; a cover glass; and a wiring board including a first main surface and a second main surface, and including wires each connected with each of the light receiving surface electrodes, back surfaces of the light receiving surface electrodes are exposed to a side of the opposite surface, distal end portions of the wires are flying leads bent at a second angle in a relation of a supplementary angle to the first angle and connected with the light receiving surface electrodes, and the second main surface at a distal end portion of the wiring board is directly fixed to the opposite surface arranged in parallel with the second main surface.

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included.

A method for producing a power electronic switching device comprising a substrate, having a power semiconductor component arranged thereon; a connection device, and terminal devices. The method comprises: Providing the substrate with an insulation ply and conductor tracks electrically insulated from one another, wherein a power semiconductor component is arranged on a conductor track and is cohesively connected thereto; Arranging the connection device embodied as a film stack; Arranging a thin pressure- and temperature-resistant and moisture-blocking insulation layer along a surface contour of the connection device and comprising a covering section and an overlap section, which overlaps the connection device circumferentially and covers the substrate in a circumferential contact region; Cohesively connecting the connection device to the substrate, whereby the connection device connects the switching device in a circuit-conforming manner internally; Connecting the covering section to the connection device; Connecting the overlap section to the contact region.

A switching device has a substrate and a power semiconductor component, comprising a connection device and a pressure device wherein the substrate has tracks electrically insulated from one another. The power semiconductor component is on one of the tracks with a first main surface and is conductively connected thereto. The device is embodied as a film composite having a conductive film and an insulating film that forms a first and a second main surface. The switching device is connected internally in a circuit-conforming manner by the connection device and a contact area of the connection device is connected to a first contact area of one of the tracks in a force-locking and electrically conductive manner. There is a pressure body projecting to the substrate and pressing onto a first section of the second main surface of the film composite.

A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package.

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.