A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.

A thin film resistor includes a high-resistance region and low-resistance regions which are formed at both ends of the high-resistance region. The high-resistance region includes first high-resistance regions and a second high-resistance region, and the first high-resistance regions are arranged at both side surfaces in a first direction in the second high-resistance region. The second high-resistance region has a higher sheet resistance than that of the first high-resistance regions.

According to an example embodiment of the present inventive concept, a semiconductor device includes a substrate. A first insulating layer is disposed on the substrate. A thin-film resistor is disposed in the first insulating layer. A capacitor structure is disposed on the first insulating layer and includes a first electrode pattern, a first dielectric pattern, a second electrode pattern, a second dielectric pattern and a third electrode pattern sequentially stacked. A first via is connected to the first electrode pattern and the third electrode pattern. A part of the first via is disposed in the first insulating layer. A second via is connected to the second electrode pattern, and a third via is connected to the thin-film resistor.

Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

The embodiments of the present disclosure provide a flexible touch substrate and a method for fabricating the same, and a touch display device and relate to touch control technology. Deformation or crack of the touch electrode pattern when the flexible touch substrate is bent, and can realize large curvature bending. The flexible touch substrate includes a flexible base substrate, touch electrode patterns disposed on a first surface of the flexible base substrate, and at least one groove on at least one of the first surface and a second surface opposite the first surface of the flexible base substrate, wherein a projection of the groove on the base substrate is within a projection of a gap between the touch electrode patterns on the base substrate.

A capacitor that prevents generation of a substrate capacitance composed of an upper electrode, a substrate, and a lower electrode. Specifically, the capacitor includes a substrate; a lower electrode disposed on the substrate; a dielectric film disposed on the lower electrode; an upper electrode disposed on a part of the dielectric film; and a first terminal electrode that is connected to the upper electrode. Moreover, the upper electrode and the first terminal electrode are formed in a region for forming the lower electrode in a plan view of the capacitor viewed from the first terminal electrode side.

A semiconductor device includes a semiconductor substrate, a semiconductor layer, an insulating film, a conductive film, a first electrode pad, a second electrode pad, and a third electrode pad. The semiconductor layer includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type opposite to the first conductivity type. The insulating film is formed on the semiconductor layer. The conductive film is formed on the second semiconductor region through the insulating film interposed therebetween. The first electrode pad is configured to be electrically connected with the first semiconductor region and is configured to be electrically connected with the power supply circuit. The second electrode pad is configured to be electrically connected with the second semiconductor region and is configured to allow a signal to be provided toward an external circuit through the second electrode pad.

An interconnect and a method of making an interconnect between one or more features on a substrate comprises: sputtering a noble metal-copper eutectic thin film under controlled power on an oxide grown or deposited on a substrate; and forming an amorphous alloy structure from the noble metal-copper eutectic thin film in the shape of the interconnect and the interconnect comprising no grain or grain boundaries without temperature sensitive resistivity.

In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.

Disclosed herein is an electronic component that includes a substrate, a functional layer formed on the substrate and having a plurality of alternately stacked conductor layers and insulating layers, and a plurality of terminal electrodes provided on an uppermost one of the insulating layers. The uppermost one of the insulating layers has a substantially rectangular planar shape and has a protruding part protruding in a planar direction from at least one side in a plan view.