An integrated circuit can include a first capacitor in a first end portion of the integrated circuit and including a first plate and a second plate, the first plate of the first capacitor being electrically coupled to ground and within a first metal layer of the integrated circuit, a first transmission line electrically coupled to the second plate of the first capacitor, the first transmission line being within a second metal layer of the integrated circuit, a second capacitor in a second end portion of the integrated circuit and including a first plate and a second plate, the first plate of the second capacitor being electrically coupled to ground and within the first metal layer of the integrated circuit, and a second transmission line electrically coupled to the second plate of the second capacitor, the second transmission line being in the second metal layer of the integrated circuit.

A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

A semiconductor device includes: a substrate; a first wiring layer arranged above the substrate; a first insulating film covering the first wiring layer; a lower oxidation preventing film arranged on the first insulating film; at least one thin-film resistor arranged on the lower oxidation preventing film; an upper oxidation preventing film arranged on the at least one thin-film resistor; a second insulating film covering the lower oxidation preventing film, the at least one thin-film resistor, and the upper oxidation preventing film; a second wiring layer arranged on the second insulating film; and a third insulating film covering the second wiring layer. The first wiring layer overlaps an end portion of the at least one thin-film resistor when viewed in a normal direction of one surface of the substrate.

Diffractive optical elements for wide field-of-view virtual reality devices and methods of manufacturing the same are disclosed. An example apparatus includes a substrate and a thin film stack including alternating layers of a first material and a second material. The thin film stack defines an annular protrusion. The annular protrusion has a stair-like profile. Top surfaces of separate ones of steps in the stair-like profile correspond to top surfaces of separate ones of the layers of the second material.

An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A flexible electronic assembly includes an electronic component, a flexible substrate and a supporting layer. The flexible substrate includes a first surface coupled to the electronic component and a second surface opposite to the first surface. The supporting layer is coupled to the second surface, and the supporting layer includes a plurality of protrusions. In a plan view of the flexible electronic assembly, one of the plurality of protrusions includes at least a rounded corner.

A display assembly includes a display component and a flexible stratum. The flexible stratum includes a first side coupled to the display component and a second side opposite to the first side. The second side includes protruding portions separate apart from each other, and one of the protruding portions includes a side section, a top section, and a tapering section extending from the side section to the top section and having a curved surface.

Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.

An interconnect and a method of making an interconnect between one or more features on a substrate comprises: sputtering a noble metal-copper eutectic thin film under controlled power on an oxide grown or deposited on a substrate; and forming an amorphous alloy structure from the noble metal-copper eutectic thin film in the shape of the interconnect and the interconnect comprising no grain or grain boundaries without temperature sensitive resistivity.