A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

A cascode transistor device includes a semiconductor substrate, and a first and a second compound semiconductor transistors. The first compound semiconductor transistor includes a first n-type doping layer, a first p-type doping layer and a second n-type doping layer sequentially disposed on the semiconductor substrate. The second compound semiconductor transistor includes a third n-type doping layer, a second p-type doping layer and a fourth n-type doping layer sequentially disposed on the second n-type doping layer. Each of these doping layers is formed with an exposed metal contact. The exposed metal contact on the second n-type doping layer is electrically connected to the exposed metal contact on the third n-type doping layer.

Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current. The high-current power required by the processor is constrained within the package substrate.

Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design. For each individualized processing chip the individualized processing chip design is provided for fabrication of the individualized processing chip according to the individualized processing chip design. The individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.

An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current. The high-current power required by the processor is constrained within the package substrate.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

A system is disclosed for the examination and inspection of integrated devices such as integrated circuits using 3-D laminography. X-rays are transmitted through the integrated device, and are incident on a photoemissive structure that absorbs x-rays and emits electrons. The electrons emitted by the photoemissive structure are shaped by an electron optical system to form a magnified image of the emitted electrons on a detector. This magnified image is then recorded and processed. In some embodiments, the incidence angle of the x-rays is varied to gather multiple images that allow internal three-dimensional structures of the integrated device to be determined using computed laminography. In some embodiments, the recorded images are compared with reference data to enable inspection for manufacturing quality control.