A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

The present technology relates to a semiconductor device and an electronic apparatus that make it possible to suppress the generation of noise in signals. A semiconductor device includes: a first semiconductor substrate on which at least a portion of a first conductor loop is formed; and a second semiconductor substrate on which a second conductor loop is formed. The second semiconductor substrate includes a first conductor layer and a second conductor layer. The first conductor layer and the second conductor layer each include a conductor. The first conductor layer and the second conductor layer are configured to cause a direction of a loop surface in which a magnetic flux is generated from the second conductor loop to be different from a direction of a loop surface in which an induced electromotive force is generated in the first conductor loop. The present technology is applicable, for example, to a CMOS image sensor.

A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a second oxide provided over the first oxide and being in contact with the side surface of the first conductor and the side surface of the second conductor; a third oxide provided over the second oxide and including regions in contact with the side surface of the first insulator and the side surface of the second insulator; a third insulator over the third oxide; and a third conductor over the third insulator.

A semiconductor device with reduced power consumption that can perform a product-sum operation is provided. The semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current/voltage converter circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit; a first terminal of the first switch is electrically connected to the first terminal of the second circuit; a second terminal of the first switch is electrically connected to an input terminal of the current/voltage converter circuit; an output terminal of the current/voltage converter circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the second switch; and a second terminal of the second switch is electrically connected to a second terminal of the second circuit. The first circuit has a function of retaining a plurality of pieces of first data and a function of making a current in an amount responsive to the sum of products of the plurality of pieces of first data and a plurality of pieces of second data flow to the first terminal of the second circuit when the plurality of pieces of second data are input to the first circuit.

The degree of freedom of an abnormality detection target location in a solid-state imaging device in which a plurality of substrates are joined is improved. A semiconductor device includes a connection line and a detection circuit. A plurality of semiconductor substrates are joined in the semiconductor device. Then, in the semiconductor device, the connection line is wired across the plurality of semiconductor substrates. The detection circuit detects the presence or absence of an abnormality in a joint surface of the plurality of semiconductor substrates based on an energization state of the connection line when enable has been set by a predetermined control signal.

A semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and first to fourth wirings. The first transistor includes a first gate and a second gate, and one of a source and a drain of the first transistor is connected to the first wiring and the second gate, and the other of the source and the drain is connected to one of a source and a drain of the second transistor and one electrode of the capacitor. A gate of the second transistor is connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring. The first wiring is supplied with a first potential, and the second wiring is supplied with a second potential and a third potential alternately. The third wiring is connected to the first gate and supplied with a first signal. The fourth wiring is connected to the gate of the second transistor and supplied with a second signal obtained by inverting the first signal.

[Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.

[Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.