An embodiment of a method of forming a programming element using a III/V semiconductor material may include forming one or more recesses in a first portion of a gate material and forming a first conductor on the one or more recesses.

In an embodiment, the method may include configuring a programming circuit to form a voltage across the one or more recesses that is greater than a breakdown voltage of the gate material underlying the one or more recesses.

An embodiment of a method of forming a programming element using a III/V semiconductor material may include forming one or more recesses in a first portion of a gate material and forming a first conductor on the one or more recesses.

In an embodiment, the method may include configuring a programming circuit to form a voltage across the one or more recesses that is greater than a breakdown voltage of the gate material underlying the one or more recesses.

A {100} indium phosphide (InP) wafer with pits distributed on the back side thereof, a method and an etching solution for manufacturing thereof are provided, wherein the pits on the back side have an elongated shape with a maximum dimension of the long axis of 65 μm, and the pits have a maximum depth of 6.0 μm. The {100} indium phosphide (InP) wafer has controllable pits distribution on the back side, thus provide a controllable emissivity of the wafer back side surface for better control of wafer back side heating during the epitaxial growth.

A {100} indium phosphide (InP) wafer with pits distributed on the back side thereof, a method and an etching solution for manufacturing thereof are provided, wherein the pits on the back side have an elongated shape with a maximum dimension of the long axis of 65 μm, and the pits have a maximum depth of 6.0 μm. The {100} indium phosphide (InP) wafer has controllable pits distribution on the back side, thus provide a controllable emissivity of the wafer back side surface for better control of wafer back side heating during the epitaxial growth.

The present disclosure provides a skyrmion diode using skyrmions as information carriers. The skyrmion diode includes a magnetic body and a conductive body. The magnetic body has a skyrmion which is used as information carrier. The conductive body is disposed on or under the magnetic body. The conductive body includes a Dzyaloshinskii-Moriya interaction (DMI) region and a defect region. The DMI region is provided to induce DMI in a region of the magnetic body corresponding to the DMI region by the spin-orbit coupling of the conductive body and magnetic moments of the magnetic body. The defect region is provided to prevent the DMI from being induced in a region of the magnetic body corresponding to the defect region.

The present disclosure provides a skyrmion diode using skyrmions as information carriers. The skyrmion diode includes a magnetic body and a conductive body. The magnetic body has a skyrmion which is used as information carrier. The conductive body is disposed on or under the magnetic body. The conductive body includes a Dzyaloshinskii-Moriya interaction (DMI) region and a defect region. The DMI region is provided to induce DMI in a region of the magnetic body corresponding to the DMI region by the spin-orbit coupling of the conductive body and magnetic moments of the magnetic body. The defect region is provided to prevent the DMI from being induced in a region of the magnetic body corresponding to the defect region.

Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm.sup.2, and a resistivity of 110.sup.7 -cm or more. The wafer may have an optical absorption of less than 5 cm.sup.1 less than 4 cm.sup.1 or less than 3 cm.sup.1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm.sup.2/V-sec or higher. The wafer may have a thickness of 500 m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.110.sup.7 cm.sup.3 or less.

A gallium-containing nitride crystals are disclosed, comprising: a top surface having a crystallographic orientation within about 5 degrees of a plane selected from a (0001) +c-plane and a (000-1) c-plane; a substantially wurtzite structure; n-type electronic properties; an impurity concentration of hydrogen greater than about 510.sup.17 cm.sup.3, an impurity concentration of oxygen between about 210.sup.17 cm.sup.3 and about 110.sup.20 cm.sup.3, an [H]/[O] ratio of at least 0.3; an impurity concentration of at least one of Li, Na, K, Rb, Cs, Ca, F, and Cl greater than about 110.sup.16 cm.sup.3, a compensation ratio between about 1.0 and about 4.0; an absorbance per unit thickness of at least 0.01 cm.sup.1 at wavenumbers of approximately 3175 cm.sup.1, 3164 cm.sup.1, and 3150 cm.sup.1, and wherein, at wavenumbers between about 3200 cm.sup.1 and about 3400 cm.sup.1 and between about 3075 cm.sup.1 and about 3125 cm.sup.1, said gallium-containing nitride crystal is essentially free of infrared absorption peaks having an absorbance per unit thickness greater than 10% of the absorbance per unit thickness at 3175 cm.

A gallium-containing nitride crystals are disclosed, comprising: a top surface having a crystallographic orientation within about 5 degrees of a plane selected from a (0001) +c-plane and a (000-1) c-plane; a substantially wurtzite structure; n-type electronic properties; an impurity concentration of hydrogen greater than about 510.sup.17 cm.sup.3, an impurity concentration of oxygen between about 210.sup.17 cm.sup.3 and about 110.sup.20 cm.sup.3, an [H]/[O] ratio of at least 0.3; an impurity concentration of at least one of Li, Na, K, Rb, Cs, Ca, F, and Cl greater than about 110.sup.16 cm.sup.3, a compensation ratio between about 1.0 and about 4.0; an absorbance per unit thickness of at least 0.01 cm.sup.1 at wavenumbers of approximately 3175 cm.sup.1, 3164 cm.sup.1, and 3150 cm.sup.1, and wherein, at wavenumbers between about 3200 cm.sup.1 and about 3400 cm.sup.1 and between about 3075 cm.sup.1 and about 3125 cm.sup.1, said gallium-containing nitride crystal is essentially free of infrared absorption peaks having an absorbance per unit thickness greater than 10% of the absorbance per unit thickness at 3175 cm.

The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.