Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

A semiconductor device includes a nitride semiconductor laminated structure formed on a substrate, a source electrode formed on the nitride semiconductor laminated structure, a drain electrode and a gate electrode, and a surface protection film covering the nitride semiconductor laminated structure. the nitride semiconductor laminated structure includes: a first nitride semiconductor layer formed on the substrate; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a composition different from the first nitride semiconductor layer. The surface protection film includes: a first insulating film formed to have contact with the gate electrode; and a second insulating film formed adjacent to the first insulating film and having a higher carbon concentration than the first insulating film.

[Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same.

[Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

A semiconductor device is provided. The semiconductor device includes a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on a portion of the barrier layer; an un-doped first capping layer on the doped compound semiconductor layer; a gate structure on the un-doped first capping layer; and source/drain structures on opposite sides of the gate structure. There is a channel region in the channel layer that is adjacent to the interface between the channel layer and the barrier layer.

An electronic device including semiconductor region located on a gallium nitride layer, two electrodes, located on either side of and insulated from the semiconductor region, the electrodes partially penetrating into the gallium nitride layer, and two lateral MOS transistors formed inside and on top of the semiconductor region.

Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first metal layer, a second metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first metal layer is disposed in the second nitride semiconductor layer. The second metal layer is disposed on the second nitride semiconductor layer. The dielectric layer is disposed between the first metal layer and the second nitride semiconductor layer and/or between the second metal layer and the second nitride semiconductor layer.

According to one embodiment, a semiconductor device includes first, second, third electrodes, first, and second semiconductor regions, a first conductive member, and an insulating member. The third electrode is between the first and second electrodes. The first semiconductor region includes first to sixth partial regions. The second semiconductor region includes first to third semiconductor portions. The first conductive member is electrically connected with a first one of the first and third electrodes. The first conductive member includes a first conductive end portion. The insulating member includes first and second nitride regions. The second semiconductor portion is between the fifth partial region and the first nitride region. The third semiconductor portion is between the sixth partial region and the second nitride region. The first nitride region includes a first nitride end portion. The first nitride end portion is in contact with the second semiconductor region.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

An embodiment of a semiconductor device includes a semiconductor substrate, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor, a control electrode formed over the semiconductor substrate between the first current carrying electrode and the second current carrying electrode, and a first dielectric layer disposed over the control electrode, and a second dielectric layer disposed over the first dielectric layer. A first opening is formed in the second dielectric layer, adjacent the control electrode and the second current-carrying electrode, having a first edge laterally adjacent to and nearer the second current-carrying electrode, and a second edge laterally adjacent to and nearer to the control electrode, and a conductive element formed over the first dielectric layer and within the first opening, wherein the portion of the conductive element formed within the first opening forms a first metal-insulator-semiconductor region within the first opening.