Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

This power supply IC is a semiconductor integrated circuit device serving as a main part for controlling a switching power supply and is formed by integrating a feedback resistor and an output feedback control unit on a single semiconductor substrate, said feedback resistor generating a feedback voltage by dividing the output voltage of the switching power supply (or the induced voltage appearing across an auxiliary winding provided on the primary side of a transformer included in an insulation-type switching power supply), said output feedback control unit performing output feedback control of the switching power supply in accordance with the feedback voltage. The feedback resistor is a polysilicon resistor having a withstand voltage of 100 V or more. A high-voltage region having higher withstand voltage in the substrate thickness direction than the other region is formed in the semiconductor substrate, and the feedback resistor is formed on the high-voltage region.

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

According to one embodiment, a semiconductor device includes first and second electrodes, first, second and third semiconductor regions, a first conductive portion, a gate electrode, and a second insulating portion. The first and second semiconductor regions are provided on the first semiconductor region. The third semiconductor regions are selectively provided respectively on the second semiconductor regions. The first conductive portion is provided inside the first semiconductor region with a first insulating portion interposed. The gate electrode is provided on the first conductive portion and the first insulating portion and separated from the first conductive portion. The gate electrode includes first and second electrode parts. The second insulating portion is provided between the first and second electrode parts. The second insulating portion includes first and second insulating parts. The second electrode is provided on the second and third semiconductor regions.

A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

A semiconductor device includes a semiconductor substrate, a first anode electrode, and a second anode electrode. The first anode electrode is disposed on the semiconductor substrate. The second anode electrode is spaced from the first anode electrode on the semiconductor substrate around the first anode electrode. At least any of a first end of the first anode electrode on a second anode electrode side and a second end of the second anode electrode on a first anode electrode side is covered with a SInSiN film.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

A normally-off vertical nitride semiconductor transistor device with low threshold voltage variation includes a drift layer containing a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film includes at least a first insulating film located at the channel region side, a second insulating film located at the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, wherein the second insulating film has charge traps with energy levels located inside the band gaps of both the first and third insulating films, and the threshold voltage is adjusted by charges accumulated in the charge traps. The threshold voltage is used to block flowing current by substantially eliminating conduction carriers of the channel region by voltage applied to the gate electrode.

An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.