Methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

Semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a doped source layer formed in the substrate; a channel pillar formed on the doped source layer; a gate structure formed on the sidewall surface of the channel pillar; a first contact layer, having a first thickness and formed at the surface of the doped source layer; and a second contact layer having a second thickness and formed on the top surface of the channel pillar. The first thickness is greater than the second thickness.

Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

An IC structure includes a plurality of first fins, a plurality of second fins, a plurality of first gate structures, a plurality of second gate structures, and a first gate contact. The first fins and the second fins are over a substrate. The first gate structures traverse the plurality of first fins. The second gate structures traverse the plurality of second fins. The first gate structures have a first gate pitch. The second gate structures have a second gate pitch wider than the first gate pitch. The first gate contact is over a first one of the second gate structures. The first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second fins.

Technologies are generally described for a four-terminal, gate-controlled, thin-film thyristor device. The thyristor device may essentially be an n-type thin-film transistor (TFT) with an additional emitter terminal. The thyristor device may exhibit an S-shaped negative differential resistance (NDR) characteristic resulting from conductance modulation. The conductance modulation may be caused by formation of a secondary channel for current flow due to an inherent structure of the device. The secondary channel may be formed in a semiconductor area within the device, the semiconductor area including a hole transporting organic semiconductor layer (HTL) and an electron transporting organic semiconductor layer (ETL). A gate terminal of the thyristor device may further allow onset of NDR characteristics to be controlled and may allow the device to be switched off.

An IC structure includes first and second semiconductor fins extending along a first direction; first and second gate electrodes respectively extending across channel regions of the first and second semiconductor fins along a second direction perpendicular to the first direction; first and second source/drain contacts extending across source/drain regions of the first and second semiconductor fins, respectively; and first source/drain via over the first source/drain contact, wherein a width of the second source/drain contact measured along the first direction is greater than a diameter of the first source/drain via.

A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.

A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.