Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

A tunnel field effect transistor includes a source region and a drain region, positioned on a substrate, a channel region positioned between the source region and the drain region and having a first length in a first direction, a gate electrode positioned on the channel region, and a gate insulating layer positioned between the channel region and the gate electrode, wherein the source region is doped with impurities of a first conductivity type and the drain region is doped with impurities of a second conductivity type that is different from the first conductivity type, and one of the source region and the drain region includes an extension region extending toward the other region, the extension region being positioned under the channel region to form a constant current independent of a gate voltage of the gate electrode.

A transistor comprises a semiconductor substrate and a barrier metal layer forming a Schottky barrier. One or more insulated gates may be positioned adjacent to an edge of the Schottky barrier. By applying a reverse bias voltage between the semiconductor substrate and the barrier metal, and applying a gate voltage between the one or more insulated gates and the barrier metal, a reverse bias current may be increased to a reverse bias conducting state. When the gate voltage is sufficient, the transistor may conduct current between the semiconductor substrate and the barrier metal. For example, voltages may be applied to an n-type substrate and an insulated gate (both relative to the barrier metal), and a current may flow from the semiconductor substrate to the barrier metal. The transistor may operate as a switch, a filter, a rectifier, an oscillator, or an amplifier.

Systems and methods for controlling one or more qubits in a quantum processor are disclosed. The system comprises a quantum processor comprising one or more spin-based qubits; and a dielectric resonator positioned in proximity to the quantum processor. The dielectric resonator provides a magnetic field. The quantum processor is positioned in a portion of the magnetic field provided by the resonator such that the portion of the magnetic field controls the spin transitions of the one or more spin-based qubits of the quantum processor.

Electrical devices are disclosed. The devices include an insulating substrate. A UO.sub.2+x crystal or oriented crystal UO.sub.2+x film is on a first portion of the substrate. The UO.sub.2+x crystal or film originates and hosts a non-equilibrium polaronic quantum phase-condensate. A first lead on a second portion of the substrate is in electrical contact with the UO.sub.2+x crystal or film. A second lead on a third portion of the surface is in electrical contact with the UO.sub.2+x crystal or film. The leads are isolated from each other. A UO.sub.2+x excitation source is in operable communication with the UO.sub.2+x crystal or film. The source is configured to polarize a region of the crystal or film thereby activating the non-equilibrium quantum phase-condensate. One source state causes the UO.sub.2+x crystal or film to be conducting. Another source state causes the UO.sub.2+x crystal or film to be non-conductive.

Systems and methods for synchronizing operation of control circuits in quantum circuit assemblies are disclosed. An example assembly for controlling operation of a qubit device includes a plurality of control circuits and an event synchronization arrangement. The plurality of control circuits may include a first and a second control circuits, configured to perform, respectively, first and second actions to control operation of the qubit device. The event synchronization arrangement may be used to control operation of the plurality of control circuits to provide to the second control circuit an indication that the first control circuit performed the first action, and to configure the second control circuit to perform the second action in response to receiving the indication that the first control circuit performed the first action. Assemblies disclosed herein provide improved control over qubits, good scalability in the number of qubits included in the device, and/or design flexibility.

The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.