An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

A complementary logic device includes i) a substrate, ii) a first semiconductor device located on the substrate and including a first channel layer, a carrier supply layer for supplying a carrier to the channel layer, and an upper cladding layer and a lower cladding layer respectively located at upper and lower portions of the channel layer, iii) a second semiconductor device located on the substrate and including a structure the same or similar to that of the first semiconductor device, iv) a source electrode located on the two semiconductors and made of a ferromagnetic body, v) a drain electrode located on the two semiconductors and made of a ferromagnetic body, and vi) a gate electrode located on the two semiconductors and located between the two electrodes so that a gate voltage is applied thereto to control a spin of electrons passing through the two channel layers.

An elementary cell for a two-dimensional array of quantum dots, said elementary cell extending along a main plane and including: a plurality of sites occupied by quantum dots capable of confining at least one spin qubit and including at least: a first quantum dot, a second quantum dot adjacent to the first quantum dot in a first direction of the main plane, and a third quantum dot adjacent to the first quantum dot in a second direction of the main plane; and a first blocking site adjacent to the second and third quantum dots, towards which a spin qubit cannot be displaced.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Systems, apparatus, and methods for initializing spin qubits with no external magnetic fields are described. An apparatus for quantum computing includes a quantum well and a pair of contacts. At least one of the contacts is formed of a ferromagnetic material. One of the contacts in the pair of contacts interfaces with a semiconductor material at a first position adjacent to the quantum well and the other contact in the pair of contacts interfaces with the semiconductor material at a second position adjacent to the quantum well. The ferromagnetic material initializes an electron or hole with a spin state prior to injection into the quantum well.

A TMR element includes a reference layer, a magnetization free layer, a tunnel barrier layer between the reference layer and the magnetization free layer, and a perpendicular magnetization inducing layer and a leakage layer stacked on a side of the magnetization free layer opposite to the tunnel barrier layer side. A magnetization direction of the reference layer is fixed along a stack direction. The perpendicular magnetization inducing layer imparts magnetic anisotropy along the stack direction to the magnetization free layer. The leakage layer is disposed on an end portion region in an in-plane direction of the magnetization free layer. The perpendicular magnetization inducing layer is disposed on at least a central region in the in-plane direction of the magnetization free layer. A resistance value of the leakage layer along the stack direction per unit area in plane is less than that of the perpendicular magnetization inducing layer.

An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, PtS.sub.2, PtSe.sub.2, WTe.sub.2, MoTe.sub.2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO.sub.3, LuFeO.sub.3, PMN-PT, PZT, AlN, or (SmBi)FeO.sub.3) adjacent to the magnet.