A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

Embodiments disclose a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, a gate dielectric layer, a first conductive layer, and a conductive plug. The gate dielectric layer is provided on the substrate, and the first conductive layer is provided on the gate dielectric layer. The conductive plug is provided on the gate dielectric layer and covers a side wall of the first conductive layer, where a projection of the conductive plug on the substrate and a projection of the gate dielectric layer on the substrate at least partially overlap. By providing the conductive plug, a breakdown current can break down a region of the gate dielectric layer corresponding to the conductive plug by means of the conductive plug. That is, a breakdown position is adjusted by controlling an overlapping position between the conductive plug and the gate dielectric layer.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to optimize device channel resistance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thin dielectric layer may be formed under an extension gate to reduce channel resistance. A thick dielectric layer may be formed under an extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

The present application discloses a method for fabricating a semiconductor device The method includes providing a substrate; forming a channel region in the substrate; forming a gate dielectric layer on the channel region; forming a gate bottom conductive layer on the gate dielectric layer; forming first impurity regions on two ends of the channel region; forming first contacts on the first impurity regions; forming programmable insulating layers on the first contacts; forming a gate via on the gate bottom conductive layer; and forming a top conductive layer on the gate via and the programmable insulating layers.

The present disclosure relates to a reconfigurable logic-in-memory device using a silicon transistor, according to the embodiment of the present disclosure, the reconfigurable logic-in-memory device using a silicon transistor comprises the silicon transistor including a drain region, a first channel region, a second channel region, a source region, and a gate region, wherein the silicon transistor performs a first channel operation while forming a first positive feedback loop in which an electron is a majority carrier in the first channel region and the second channel region depending on a level of a gate voltage V.sub.in applied through the gate region or performs a second channel operation while forming a second positive feedback loop in which a hole is a majority carrier in the first channel region and the second channel region depending on the level of a gate voltage V.sub.in applied through the gate region.

Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.