A device includes at least one photoconductor configured for exhibiting an electrical resistance R.sub.photo dependent on an illumination of a light-sensitive region of the at least one photoconductor and at least one photoconductor readout circuit. The photoconductor readout circuit is configured for determining a differential voltage related to changes of the electrical resistance R.sub.photo of the photoconductor. The photoconductor readout circuit includes at least one bias voltage source configured for applying at least one periodically modulated bias voltage to the photoconductor such that the electric output changes its polarity at least once. The device further includes at least one electrical circuit configured to balance the differential voltage at a given illumination level.

Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

The present disclosure is a heat blocking device 101 that includes a heat blocking film 10 including: a particle that absorbs an infrared ray and generates an electron and a hole; and an acceptor that receives the electron or the hole from the particle. A charge carrier selected from the electron and the hole is released from the heat blocking film 10 to an outside of the device. The heat blocking device 101 can function as a “heat removing” device. The heat blocking film 10 may be a single-layer film or a multilayer film.

Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

An optical sensor includes at least one photodetector configured to be reverse biased at a voltage exceeding a breakdown voltage by an excess bias voltage. At least one control unit is configured to adjust the reverse bias of the at least one photodetector. A method of operating an optical sensor is also disclosed.

There is set forth herein an optoelectrical system comprising: a conductive path for supplying an input voltage to a photonics device, wherein the conductive path comprises a base structure through via extending through a substrate and a photonics structure through via, the photonics structure through via extending through a photonics device dielectric stack. There is set forth herein an optoelectrical system comprising: a second structure fusion bonded to an interposer base dielectric stack of a first structure. There is set forth herein a method comprising: fabricating a second wafer built structure using a second wafer, the second wafer built structure defining a photonics structure and having a photonics device integrated into a photonics device dielectric stack of the second wafer based structure; and wafer scale bonding the second wafer built structure to a first wafer built structure.

A camera module optical system is provided, having a main axis, including an optical module and an adjustment assembly. The optical module is configured to hold an optical element having an optical axis. The adjustment assembly is configured to adjust the optical axis of the optical module parallel to the main axis. The optical module and the adjustment assembly are arranged along the main axis, wherein the adjustment assembly does not overlap the optical module when viewed in a first direction that is perpendicular to the main axis.

An imaging device capable of executing image processing is provided. A structure is employed in which a photoelectric conversion element, a first transistor, a second transistor, and an inverter circuit are included; one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the one of the source and the drain of the second transistor is electrically connected to an input terminal of the inverter circuit; and data obtained by photoelectric conversion is binarized and output.

An apparatus comprises a ground plane (2), an integrated circuit chip (1) disposed on the ground plane (2), the integrated circuit chip (1) comprising one or more electrically conductive layers (10) encircling a periphery of the integrated circuit chip (1), and a plurality of bondwires (9) electrically coupling the one or more electrically conductive layers (10) to the ground plane (2).