A method for manufacturing an optical-semiconductor device, including forming a plurality of first and second electrically conductive members that are disposed separately from each other on a support substrate; providing a base member formed from a light blocking resin between the first and second electrically conductive members; mounting an optical-semiconductor element on the first and/or second electrically conductive member; covering the optical-semiconductor element by a sealing member formed from a translucent resin; and obtaining individual optical-semiconductor devices after removing the support substrate.

A division device includes a platform, a withstanding element and a pressure element. The platform has a platform surface. The withstanding element, located on the platform surface, has at least one shrink-top-type withstanding structure protruding from the platform surface and extending along a withstanding line. The shrink-top-type withstanding structure is to withstand the solar cell sheet. The pressure element, located above the platform, has two forcing portions protruding toward the platform. While the solar cell sheet is under dividing, a back surface of the solar cell sheet opposing to the front surface is arranged to face the shrink-top-type withstanding structure by aligning the trench with the withstanding line, and then the two forcing portions are introduced to apply predetermined depression individually onto the two solar cell units, such that the solar cell sheet are divided into the two separate solar cell units.

A division device includes a platform, a withstanding element and a pressure element. The platform has a platform surface. The withstanding element, located on the platform surface, has at least one shrink-top-type withstanding structure protruding from the platform surface and extending along a withstanding line. The shrink-top-type withstanding structure is to withstand the solar cell sheet. The pressure element, located above the platform, has two forcing portions protruding toward the platform. While the solar cell sheet is under dividing, a back surface of the solar cell sheet opposing to the front surface is arranged to face the shrink-top-type withstanding structure by aligning the trench with the withstanding line, and then the two forcing portions are introduced to apply predetermined depression individually onto the two solar cell units, such that the solar cell sheet are divided into the two separate solar cell units.

An optoelectronic semiconductor component includes an optoelectronic semiconductor chip; and an electrical connection point that contacts the optoelectronic semiconductor chip, wherein the electrical connection point covers the optoelectronic semiconductor chip on the bottom thereof at least in some areas, the electrical connection point includes a contact layer facing toward the optoelectronic semiconductor chip, the electrical connection point includes at least one barrier layer arranged on a side of the contact layer facing away from the optoelectronic semiconductor chip, the electrical connection point includes a protective layer arranged on the side of the at least one barrier layer facing away from the contact layer, the layers of the electrical connection point are arranged one on top of another along a stack direction, and the stack direction runs perpendicular to a main extension plane of the optoelectronic semiconductor chip.

An optoelectronic semiconductor component includes an optoelectronic semiconductor chip; and an electrical connection point that contacts the optoelectronic semiconductor chip, wherein the electrical connection point covers the optoelectronic semiconductor chip on the bottom thereof at least in some areas, the electrical connection point includes a contact layer facing toward the optoelectronic semiconductor chip, the electrical connection point includes at least one barrier layer arranged on a side of the contact layer facing away from the optoelectronic semiconductor chip, the electrical connection point includes a protective layer arranged on the side of the at least one barrier layer facing away from the contact layer, the layers of the electrical connection point are arranged one on top of another along a stack direction, and the stack direction runs perpendicular to a main extension plane of the optoelectronic semiconductor chip.

A functional panel is provided. The functional panel includes a first substrate, a second substrate, a bonding layer, a functional element, a protective layer, and a terminal. The bonding layer is positioned between the first and second substrates. The functional element is surrounded by the first substrate, the second substrate, and the bonding layer. The terminal is electrically connected to the functional element and provided not to overlap with one of the first and second substrates. The protective layer is provided to be in contact with side surfaces of the first and second substrates and an exposed surface of the bonding layer. A surface of the terminal is partly exposed without being covered with the protective layer. The surface of the terminal partly includes a material having a lower ionization tendency than hydrogen.

A functional panel is provided. The functional panel includes a first substrate, a second substrate, a bonding layer, a functional element, a protective layer, and a terminal. The bonding layer is positioned between the first and second substrates. The functional element is surrounded by the first substrate, the second substrate, and the bonding layer. The terminal is electrically connected to the functional element and provided not to overlap with one of the first and second substrates. The protective layer is provided to be in contact with side surfaces of the first and second substrates and an exposed surface of the bonding layer. A surface of the terminal is partly exposed without being covered with the protective layer. The surface of the terminal partly includes a material having a lower ionization tendency than hydrogen.

A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

A sensing device includes a substrate, two chips, and a shielding structure. The two chips are respectively defined as an emitting chip and a receiving chip. The emitting chip can emit a sensing light beam, the receiving chip can receive the sensing light beam, and the two chips are fixed in position on the substrate at intervals. At least one of the chips is electrically connected to the substrate through at least one wire, and a position where the wire is connected to the substrate is located between the two chips. The shielding structure is formed on the substrate. The shielding structure is located between the two chips, and the shielding structure covers the wire and a portion of the chip connected to the wire. Compared with the conventional photo-plethysmography sensor, the sensing device has the advantage of a smaller size.

A sensing device includes a substrate, two chips, and a shielding structure. The two chips are respectively defined as an emitting chip and a receiving chip. The emitting chip can emit a sensing light beam, the receiving chip can receive the sensing light beam, and the two chips are fixed in position on the substrate at intervals. At least one of the chips is electrically connected to the substrate through at least one wire, and a position where the wire is connected to the substrate is located between the two chips. The shielding structure is formed on the substrate. The shielding structure is located between the two chips, and the shielding structure covers the wire and a portion of the chip connected to the wire. Compared with the conventional photo-plethysmography sensor, the sensing device has the advantage of a smaller size.