Patent classifications
H01L31/1804
Semi-conductor wafers longer than industry standard square
A semiconductor wafer is as wide as the industry standard width A (presently 156 mm+/−1 mm) and is longer than the industry standard A by at least 1 mm and as much as the standard equipment can reasonably accommodate, presently approximately 3-20 mm and potentially longer, thus, gaining significant additional surface area for sunlight absorption. Modules may be composed of a plurality of such larger wafers. Such wafers can be processed in conventional processing equipment that has a wafer retaining portion of industry standard size A and a configuration that also accommodates a wafer with a perpendicular second edge longer than A by at least 1 and typically 3-20 mm. Wet bench carriers and transport and inspection stations can be so used.
SOLAR MODULE HAVING A PLURALITY OF STRINGS CONFIGURED FROM A FIVE STRIP CELL
In an example, the present invention provides a method of manufacturing a solar module. The method includes providing a substrate member having a surface region, the surface region comprising a spatial region, a first end strip comprising a first edge region and a first interior region, the first interior region comprising a first bus bar, a plurality of strips, a second end strip comprising a second edge region and a second interior region, the second edge region comprising a second bus bar, the first end strip, the plurality of strips, and the second end strip arranged in parallel to each other and occupying the spatial region such that the first end strip, the second end strip, and the plurality of strips consists of a total number of five (5) strips. The method includes separating each of the plurality of strips, arranging the plurality of strips in a string configuration, and using the string in the solar module.
Germanium based focal plane array for the short infrared spectral regime
Light detecting structures comprising a Si base having a pyramidal shape with a wide incoming light-facing pyramid bottom and a narrower pyramid top and a Ge photodiode formed on the Si pyramid top, wherein the Ge photodiode is operable to detect light in the short wavelength infrared range, and methods for forming such structures. A light detecting structure as above may be repeated spatially and fabricated in the form of a focal plane array of Ge photodetectors on silicon.
FRONT CONTACT SOLAR CELL WITH FORMED EMITTER
A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.
Non-diffusion type photodiode
A non-diffusion type photodiode is described and has: a substrate, a buffer layer, a light absorption layer, an intermediate layer, and a multiplication/window layer. The buffer layer is disposed on the substrate. The light absorption layer is disposed on the buffer layer. The intermediate layer is disposed on the light absorption layer and has a first boundary, wherein the intermediate layer is an I-type semiconductor layer or a graded refractive index layer. The multiplication/window layer is disposed on the intermediate layer and has a second boundary, wherein in a top view, the first boundary surrounds the second boundary, and a distance between the first boundary and the second boundary is greater than or equal to 1 micrometer. The non-diffusion type photodiode can reduce generation of dark current.
High efficiency solar cell and method for manufacturing high efficiency solar cell
A solar cell including a semiconductor substrate having a first conductivity type an emitter region, having a second conductivity type opposite to the first conductivity type, on a first main surface of the semiconductor substrate an emitter electrode which is in contact with the emitter region a base region having the first conductivity type a base electrode which is in contact with the base region and an insulator film for preventing an electrical short-circuit between the emitter region and the base region, wherein the insulator film is made of a polyimide, and the insulator film has a C.sub.6H.sub.11O.sub.2 detection count number of 100 or less when the insulator film is irradiated with Bi.sub.5.sup.++ ions with an acceleration voltage of 30 kV and an ion current of 0.2 pA by a TOF-SIMS method. The solar cell can have excellent weather resistance and high photoelectric conversion characteristics.
METHOD FOR THERMALLY ACTIVATING A PASSIVATION LAYER
A method for thermally activating a passivation layer disposed on a photovoltaic cell. The photovoltaic cell includes a first face, a second face opposite to the first face, and side surfaces connecting the first and second faces. The passivation layer covers at least one of the side surfaces of the photovoltaic cell. The method includes exposing the first face to electromagnetic radiation emitted by a radiation source. The electromagnetic radiation is applied to the first face along a line. The line sweeps at least part of the first face and is oriented relative to the first face so as to provide an overheating zone encompassing at least part of the passivation layer.
MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES
Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
WAVEGUIDE PHOTODETECTORS FOR SILICON PHOTONIC INTEGRATED CIRCUITS
A photodetector structure over a partial length of a silicon waveguide structure within a photonic integrated circuit (PIC) chip. The photodetector structure is embedded within a cladding material surrounding the waveguide structure. The photodetector structure includes an absorption region, for example comprising Ge. A sidewall of the cladding material may be lined with a sacrificial spacer. After forming the absorption region, the sacrificial spacer may be removed and passivation material formed over a sidewall of the absorption region. Between the absorption region an impurity-doped portion of the waveguide structure there may be a carrier multiplication region, for example comprising crystalline silicon. If present, edge facets of the carrier multiplication region may be protected by a spacer material during the formation of an impurity-doped charge carrier layer. Occurrence of edge facets may be mitigated by embedding a portion of the photodetector structure with a thickness of the waveguide structure.
Method for manufacture and structure of multiple electrochemistries and energy gathering components within a unified structure
A method for using an integrated battery and device structure includes using two or more stacked electrochemical cells integrated with each other formed overlying a surface of a substrate. The two or more stacked electrochemical cells include related two or more different electrochemistries with one or more devices formed using one or more sequential deposition processes. The one or more devices are integrated with the two or more stacked electrochemical cells to form the integrated battery and device structure as a unified structure overlying the surface of the substrate. The one or more stacked electrochemical cells and the one or more devices are integrated as the unified structure using the one or more sequential deposition processes. The integrated battery and device structure is configured such that the two or more stacked electrochemical cells and one or more devices are in electrical, chemical, and thermal conduction with each other.