Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.

An avalanche diode including a gain region and a readout structure including an n-type (p-type) region having electrically isolated segments each including implanted regions; a p-type (n-type) region; and a first electrode on each of the segments. The gain region includes a p-n junction buried between the n-type region and the p-type region: an n.sup.+-type region having a higher n-type dopant density than the n-type region; a p.sup.+-type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n.sup.+-type region and the p.sup.+-type region. A bias between the first electrodes and a second electrode (ohmically contacting the p-type (n-type) region) reverse biases the p-n junction. Electrons generated in response to electromagnetic radiation or charged particles generate additional electrons m the gain region through impact ionization but the segmented region comprises a low field region isolating the gain region from the first electrodes.

A tandem photovoltaic device includes a silicon photovoltaic cell having a silicon layer, a perovskite photovoltaic cell having a perovskite layer, and an intermediate layer between a rear side of the perovskite photovoltaic cell and a front (sunward) side of the silicon photovoltaic cell. The front side of the silicon layer has a textured surface, with a peak-to-valley height of structures in the textured surface of less than 1 μm or less than 2 μm. The textured surface is planarized by the intermediate layer or a layer of the perovskite photovoltaic cell. Forming the tandem photovoltaic device includes texturing a silicon containing layer of a silicon photovoltaic cell and operatively coupling a perovskite photovoltaic cell comprising a perovskite layer to the silicon photovoltaic cell, thereby forming a tandem photovoltaic device and planarizing the textured surface of the silicon containing layer of the silicon photovoltaic cell.

The present application provides a method for manufacturing a monocrystalline silicon sheet, including: cutting a monocrystalline silicon rod along a radial or an axial direction of the monocrystalline silicon rod to obtain a monocrystalline silicon substrate; etching a porous silicon structure on a top surface and a bottom surface of the monocrystalline silicon substrate by wet etching; depositing a monocrystalline silicon thin layer on the porous silicon structure by chemical vapor deposition, so that a thickness of the monocrystalline silicon thin layer reaches a predetermined value; and striping the monocrystalline silicon thin layer from the porous silicon structure to obtain the monocrystalline silicon sheet. In the present application, the production capacity of directly manufacturing a single crystal silicon wafer by a chemical vapor deposition method can be improved, and a process for manufacturing a silicon wafer is combined with the process of a diffusion emitter conventionally belonging to cell manufacturing, so that a manufacturing cost of a solar monocrystalline silicon cell is significantly reduced.

Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and a one-dimensional size of the top surface of the outermost first substructure is less than or equal to 45 μm; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer, the doped conductive layer includes a P-type doped conductive layer and an N-type doped conductive layer; and a second passivation layer located on a surface of the doped conductive layer.

An electronic device includes a substrate, a plurality of electronic components and a conductive material. The electronic components are arranged on the substrate, and the electronic components respectively include a lower electrode, a semiconductor layer and an upper electrode, and they are sequentially stacked on the substrate. The electronic components share the semiconductor layer, and the semiconductor layer forms a plurality of connecting channels through the semiconductor layer. The connecting channels are located between the upper electrode of the first electronic component in the electronic components and the lower electrode of the second electronic component in the electronic components. These connecting channels are processed by lasers of different powers. The conductive material is arranged in the connecting channel so that the upper electrode of the first electronic component is electrically connected to the lower electrode of the second electronic component.

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: a spiral fin structure comprising semiconductor substrate material and dielectric material; a photosensitive semiconductor material over sidewalls and a top surface of the spiral fin structure, the photosensitive semiconductor material positioned to capture laterally emitted incident light; a doped semiconductor material above the photosensitive semiconductor material; and contacts electrically contacting the semiconductor substrate material and the doped semiconductor material from a top surface thereof.

The invention relates to a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell. The object of the invention is to propose a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell, in which the effects on materials caused by irradiation of the sun-facing side are further minimized. In addition, the method should also be applicable to silicon solar cells in which the emitter layer has a high sheet resistance. This object is achieved by first providing the silicon solar cell with the emitter layer, the contact grid and a rear contact, and electrically connecting the contact grid to one pole of a voltage source, then a contacting device that is electrically connected to the other pole of the voltage source is connected to the rear contact, and with the voltage source, a voltage is applied directed contrary to the forward direction of the silicon solar cell that is less than the breakdown voltage of the silicon solar cell and, when applying this voltage, a point light source is guided over the sun-facing side of the silicon solar cell and thereby a section of a subsection of the sun-facing side is illuminated and thus a current flow is induced in the subsection where the current flow relative to the section has a current density of 200 A/cm.sup.2 to 20,000 A/cm.sup.2 and acts on the subsection for 10 ns to 10 ms.

Provided are a solar cell, a method for manufacturing a solar cell and a photovoltaic module. The solar cell includes a semiconductor substrate including a surface having a first texture structure and a first passivation layer located on the first texture structure of the semiconductor substrate. The first texture structure includes a pyramid-shaped microstructure, a length of a bevel edge of the pyramid-shaped microstructure is C μm, and 0.4≤C≤1.9. A non-uniformity of the first passivation layer is N≤4%, and N=(D.sub.max−D.sub.min)/D.sub.max. D.sub.max is a maximum thickness of the first passivation layer on the pyramid-shaped microstructure, and D.sub.min is a minimum thickness of the first passivation layer on the pyramid-shaped microstructure.

An optoelectronic device including at least an emissive component including at least a first electrode, a second electrode, and an emissive element disposed between an emissive face of the optoelectronic device and the second electrode, a photodetector component such that the second electrode of the emissive component is disposed between the photodetector component and the emissive element. The emissive component and the photodetector component are superimposed one above the other, and the second electrode has at least one hole passing through it, disposed vertically in line with at least a part of a detection surface of the photodetector component and/or a part of the detection surface of the photodetector component is not disposed vertically in line with the second electrode and form a ring located at the external edges of the detection surface of the photodetector component.