An optoelectronic semiconductor light emitting device configured to emit light having a wavelength in the range from about 150 nm to about 425 nm is disclosed. In embodiments, the device comprises a substrate having at least one epitaxial semiconductor layer disposed thereon, wherein each of the one or more epitaxial semiconductor layers comprises a metal oxide. Also disclosed is an optoelectronic semiconductor device for generating light of a predetermined wavelength comprising a substrate and an optical emission region. The optical emission region has an optical emission region band structure configured for generating light of the predetermined wavelength and comprises one or more epitaxial metal oxide layers supported by the substrate.

A semiconductor device is provided, which includes an active structure, a first semiconductor layer, a second semiconductor layer, an intermediate layer, a transition layer and a contact layer. The active structure has two sides and includes an active region. The first semiconductor layer and the second semiconductor layer respectively located on the two sides of the active structure. The intermediate layer is located between the second semiconductor layer and the active structure. The transition layer is located on the second semiconductor layer. The contact layer is located on the transition layer.

In some embodiments, a semiconductor structure includes: a first region comprising a first epitaxial oxide material; a second region comprising a second epitaxial oxide material; and a chirp layer located between the first and the second regions. The chirp layer can include alternating layers of a plurality of wide bandgap epitaxial oxide material layers (WBG layers) and a plurality of narrow bandgap epitaxial oxide material layers (NBG layers), wherein thicknesses of the NBG layers and the WBG layers change throughout the chirp layer. The WBG layer can comprise (Al.sub.x1Ga.sub.1−x1).sub.y1O.sub.z1, wherein x1 is from 0 to 1, wherein y1 is from 1 to 3, and wherein z1 is from 2 to 4. The NBG layer can comprise (Al.sub.x2Ga.sub.1x−2).sub.y2O.sub.z2, wherein x2 is from 0 to 1, wherein y2 is from 1 to 3, and wherein z2 is from 2 to 4, and wherein x1 and x2 are different from one another.

In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Heterostructures include a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions.

Embodiments disclose LEDs that operate using impact ionization. Devices include a first conductivity type layer having a first conductivity type, a first intrinsic layer, a charge layer, an impact ionization layer, and a contact layer. The charge layer has a net charge of the first conductivity type and has a material comprising a polar oxide or a non-polar oxide. The charge layer forms a barrier for transporting carriers of the first conductivity type until a bias is applied between the first conductivity type layer and the contact layer to flatten the barrier.

There is provided an optoelectronic device having an operation range reaching and exceeding 4 μm. The optoelectronic device includes a silicon or a silicon-based substrate and a heterostructure at least partially extending over the substrate. The heterostructure includes a stack of coextending photoactive layers and each photoactive layer includes one or two group IV elements. The photoactive layers are configured for absorbing and/or emitting short-wave infrared and mid-wave infrared radiation. In some embodiments, the short-wave infrared and mid-wave infrared radiation is in a wavelength range extending from about 1 μm to about 8 μm. Methods for manufacturing such an optoelectronic device and device processing are also provided. The methods include forming a heterostructure on a substrate, releasing the heterostructure from the substrate to form a relaxed membrane and transferring the relaxed membrane on a host substrate.

Shockley-Read-Hall (SRH) generation and/or recombination in heterojunction devices is suppressed by unconventional doping at or near the heterointerface. The effect of this doping is to shift SRH generation and/or recombination preferentially into the wider band gap material of the heterojunction. This reduces total SRH generation and/or recombination in the device by decreasing the intrinsic carrier concentration n.sub.i at locations where most of the SRH generation and/or recombination occurs. The physical basis for this effect is that the SRH generation and/or recombination rate tends to decrease as n.sub.i around the depletion region decreases, so decreasing the effective n.sub.i in this manner is a way to decrease SRH recombination.

An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (Al.sub.xGa.sub.1-x).sub.yO.sub.z, wherein 0≤x≤1, 1≤y≤3, and 2≤z≤4, wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a Pna21 space group, and wherein the (Al.sub.xGa.sub.1-x)O.sub.z comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.