In an embodiment an optoelectronic device includes a carrier and a plurality of semiconductor chips fastened on the carrier by a connector, wherein each semiconductor chip has at least one contact pad on a main surface facing away from the carrier, wherein each contact pad is contacted electrically by an interconnecting track, and wherein the interconnecting track is guided over an edge of the main surface of the semiconductor chip onto the carrier.

A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material, in which a width of an upper end of the upper conductive material is greater than a width of the corresponding upper conductive material.

An electronic part includes: a chip part having a first main surface and a second main surface opposite to the first main surface, a wiring portion being derived from the chip part; and a substrate having a pad forming surface, pads to which the wiring portion can be connected being formed on the pad forming surface, in which a gap is formed between the second main surface and the pad forming surface while the wiring portion is connected to a predetermined pad of the pads.

A display device and a manufacturing method of the display device are provided. A display device includes a conductive line disposed on a substrate, a first capacitor electrode disposed on the conductive line and electrically connected to the conductive line, a passivation layer disposed on the first capacitor electrode, a first electrode disposed on the passivation layer and at least partially overlapping the first capacitor electrode in a plan view, a second electrode spaced apart from the first electrode, the second electrode and the first electrode being disposed on a same layer, and light emitting elements disposed between the first electrode and the second electrode.

This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.

A micro-light emitting diode (LED) display panel and a method of forming the display panel, the micro-LED display panel having a monolithically grown micro-structure including a first color micro-LED that is a first color nanowire LED, and a second color micro-LED that is a second color nanowire LED.

A method of making a surface-mountable pixel engine package comprises providing an array of spaced-apart conductive pillars and an insulating mold compound laterally disposed between the conductive pillars on a substrate together defining a planarized surface. Pixel engines comprising connection posts are printed to the conductive pillars so that each of the connection posts is in electrical contact with one of the conductive pillars. The pixel engines are tested to determine known-good pixel engines. An optically clear mold compound is provided over the planarized surface and tested pixel engines. Optically clear mold compound is adhered to a tape and the substrate is removed. The optically clear mold compound, the insulating mold compound, the conductive pillars, the optically clear mold compound, and the tested pixel engines are singulated to provide pixel packages that comprise the pixel engines and the known-good pixel engines are transferred to a reel or tray.

Herein disclosed are a wafer, a wafer testing system, and a method thereof. Said wafer testing method comprises the following steps. First, an incident light is provided toward a wafer. And, a wafer surface image corresponded to the wafer is generated. Then, determining whether the wafer surface image has a plurality of first strips and a plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical. When the wafer surface image has the plurality of first strips and the plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical, a qualified signal corresponded to the wafer is provided.

A drive backboard, a manufacturing method thereof, a display panel and a display device are provided. The drive backboard includes a plurality of pixel units and a plurality of spare electrode groups. Each pixel unit includes m subpixel units, and m is a positive integer greater than or equal to 2. Each spare electrode group includes two first spare electrodes and one second spare electrode; two adjacent i.sup.th subpixel units respectively use one first spare electrode in each spare electrode group and share one second spare electrode in each spare electrode group, where i is a positive integer from 1 to m.

A light emitting diode includes an active layer, a first type semiconductor layer, a second type semiconductor layer and a pick-up layer. The first type semiconductor layer and the second type semiconductor layer are located on two opposite sides of the active layer respectively. The pick-up layer is located on the second type semiconductor layer, wherein the pick-up layer has a patterned outer surface to serve as a grabbed surface during transferring.