An epitaxial wafer of a light-emitting chip, a method for manufacturing an epitaxial wafer, and a light-emitting chip are provided. A light-emitting layer (5) of an active region of the epitaxial wafer of the light-emitting chip includes at least one superlattice (51), and each superlattice includes: a quantum well sub-layer (511) and a stress conversion sub-layer (512) which is formed on the quantum well sub-layer (511) and enables the quantum well sub-layer (511) to be converted from compressive strain to tensile strain, and the stress conversion sub-layer (512) and the quantum well sub-layer (511) form a two-dimensional electron gas.

A semiconductor structure (100) comprising: a substrate (102), a first layer (106) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N disposed on the substrate, stacks (107, 109) of several second and third layers (108, 110) alternating against each other, between the substrate and the first layer, a fourth layer (112) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N, between the stacks, a relaxation layer of AlN disposed between the fourth layer and one of the stacks, and, in each of the stacks: the level of Ga of the second layers increases from one layer to the next in a direction from the substrate to the first layer, the level of Ga of the third layers is constant or decreasing from one layer to the next in said direction, the average mesh parameter of each group of adjacent second and third layers increasing from one group to the next in said direction, the thickness of the second and third layers is less than 5 nm.

A semiconductor structure (100) comprising: a substrate (102), a first layer (106) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N disposed on the substrate, stacks (107, 109) of several second and third layers (108, 110) alternating against each other, between the substrate and the first layer, a fourth layer (112) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N, between the stacks, a relaxation layer of AlN disposed between the fourth layer and one of the stacks, and, in each of the stacks: the level of Ga of the second layers increases from one layer to the next in a direction from the substrate to the first layer, the level of Ga of the third layers is constant or decreasing from one layer to the next in said direction, the average mesh parameter of each group of adjacent second and third layers increasing from one group to the next in said direction, the thickness of the second and third layers is less than 5 nm.

A light-emitting diode includes a material structure of barrier in the light-emitting well region to improve restriction capacity of electron holes, improving light-emitting efficiency of the LED chip under high temperature. The LED structure includes a Type I semiconductor layer, a Type II semiconductor layer and an active layer between the both, wherein, the active layer is a multi-quantum well structure alternatively composed of well layers and barrier layers, in which, the first barrier layer is a first AlGaN gradient layer in which aluminum components gradually increase in the direction from the Type I semiconductor layer to the quantum well, and the barrier layer at the middle of well layers is an AlGaN/GaN/AlGaN multi-layer barrier layer, and the last barrier layer is a second AlGaN gradient layer in which aluminum components gradually decrease in the direction from the quantum well to the Type II semiconductor layer.

A light-emitting diode includes a material structure of barrier in the light-emitting well region to improve restriction capacity of electron holes, improving light-emitting efficiency of the LED chip under high temperature. The LED structure includes a Type I semiconductor layer, a Type II semiconductor layer and an active layer between the both, wherein, the active layer is a multi-quantum well structure alternatively composed of well layers and barrier layers, in which, the first barrier layer is a first AlGaN gradient layer in which aluminum components gradually increase in the direction from the Type I semiconductor layer to the quantum well, and the barrier layer at the middle of well layers is an AlGaN/GaN/AlGaN multi-layer barrier layer, and the last barrier layer is a second AlGaN gradient layer in which aluminum components gradually decrease in the direction from the quantum well to the Type II semiconductor layer.

A method of manufacturing a LED precursor and a LED precursor is provided. The LED precursor is manufactured by forming a monolithic growth stack having a growth surface and forming a monolithic LED stack on the growth surface. The monolithic growth stack comprises a first semiconducting layer comprising a Group III-nitride, a second semiconducting layer, and third semi-conducting layer. The second semiconducting layer comprises a first Group III-nitride including a donor dopant such that the second semiconducting layer has a donor density of at least 5×1018 cm-3. The second semiconducting layer has an areal porosity of at least 15% and a first in-plane lattice constant. The third semiconducting layer comprises a second Group III-nitride different to the first Group-III-nitride. The monolithic growth stack comprises a mesa structure comprising the third semiconducting layer such that the growth surface comprises a mesa surface of third semiconducting layer and a sidewall surface of the third semiconducting layer encircling the mesa surface. The sidewall surface of the third semiconducting layer is inclined relative to the mesa surface. The mesa surface of the third semiconducting layer has a second in-plane lattice constant which is greater than the first in-plane lattice constant.

A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial crystalline layer to enable strain relaxation in the second epitaxial crystalline layer by plastic deformation of bonds in the first epitaxial crystalline layer and/or at the interface between the first epitaxial crystalline layer and the second epitaxial crystalline layer; and forming one or more channels comprising a conductive material through at least the first epitaxial crystalline layer and the second epitaxial crystalline layer thereby to enable electrical connection to the crystalline template layer through the first epitaxial crystalline layer and the second epitaxial crystalline layer.

A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial crystalline layer to enable strain relaxation in the second epitaxial crystalline layer by plastic deformation of bonds in the first epitaxial crystalline layer and/or at the interface between the first epitaxial crystalline layer and the second epitaxial crystalline layer; and forming one or more channels comprising a conductive material through at least the first epitaxial crystalline layer and the second epitaxial crystalline layer thereby to enable electrical connection to the crystalline template layer through the first epitaxial crystalline layer and the second epitaxial crystalline layer.

An embodiment includes a semiconductor device including a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulation layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer; a second electrode disposed on the second conductive semiconductor layer; a first cover electrode disposed on the first electrode; a second cover electrode disposed on the second electrode; and a second insulation layer extending from an upper surface of the first cover electrode to an upper surface of the second cover electrode. The semiconductor structure includes a first surface extending from an upper surface of the first conductive semiconductor layer where the first electrode is disposed to a side surface of the active layer and an upper surface of the second conductive semiconductor where the second electrode is disposed. The first insulation layer is disposed on the first surface to be spaced apart from the first electrode. The first insulation layer is disposed on the first surface to overlap with the first cover electrode in a first direction perpendicular to the upper surface of the first conductive semiconductor layer.

An embodiment includes a semiconductor device including a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulation layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer; a second electrode disposed on the second conductive semiconductor layer; a first cover electrode disposed on the first electrode; a second cover electrode disposed on the second electrode; and a second insulation layer extending from an upper surface of the first cover electrode to an upper surface of the second cover electrode. The semiconductor structure includes a first surface extending from an upper surface of the first conductive semiconductor layer where the first electrode is disposed to a side surface of the active layer and an upper surface of the second conductive semiconductor where the second electrode is disposed. The first insulation layer is disposed on the first surface to be spaced apart from the first electrode. The first insulation layer is disposed on the first surface to overlap with the first cover electrode in a first direction perpendicular to the upper surface of the first conductive semiconductor layer.