Patent classifications
H01L33/14
MICRO LIGHT EMITTING DIODE CHIP
A micro light emitting diode chip including a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first-type electrode, and a second-type electrode is provided. The first-type semiconductor layer has a first high-concentration doping region and a first low-concentration doping region. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first-type electrode is directly contacted and electrically connected to the first high-concentration doping region. The second-type electrode is electrically connected to the second-type semiconductor layer.
MICRO LIGHT EMITTING DIODE CHIP
A micro light emitting diode chip including a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first-type electrode, and a second-type electrode is provided. The first-type semiconductor layer has a first high-concentration doping region and a first low-concentration doping region. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first-type electrode is directly contacted and electrically connected to the first high-concentration doping region. The second-type electrode is electrically connected to the second-type semiconductor layer.
Epitaxial Wafer of Light-Emitting Chip, Method for Manufacturing Epitaxial Wafer, and Light-Emitting Chip
An epitaxial wafer of a light-emitting chip, a method for manufacturing an epitaxial wafer, and a light-emitting chip are provided. A light-emitting layer (5) of an active region of the epitaxial wafer of the light-emitting chip includes at least one superlattice (51), and each superlattice includes: a quantum well sub-layer (511) and a stress conversion sub-layer (512) which is formed on the quantum well sub-layer (511) and enables the quantum well sub-layer (511) to be converted from compressive strain to tensile strain, and the stress conversion sub-layer (512) and the quantum well sub-layer (511) form a two-dimensional electron gas.
Epitaxial Wafer of Light-Emitting Chip, Method for Manufacturing Epitaxial Wafer, and Light-Emitting Chip
An epitaxial wafer of a light-emitting chip, a method for manufacturing an epitaxial wafer, and a light-emitting chip are provided. A light-emitting layer (5) of an active region of the epitaxial wafer of the light-emitting chip includes at least one superlattice (51), and each superlattice includes: a quantum well sub-layer (511) and a stress conversion sub-layer (512) which is formed on the quantum well sub-layer (511) and enables the quantum well sub-layer (511) to be converted from compressive strain to tensile strain, and the stress conversion sub-layer (512) and the quantum well sub-layer (511) form a two-dimensional electron gas.
LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING LIGHT-EMITTING ELEMENT
A nitride-based semiconductor light-emitting element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type; a carrier blocking layer of the second conductivity type, provided on a surface of the second semiconductor layer closer to the first semiconductor layer; and a light-emitting layer region having a light-emitting layer, provided between the first semiconductor layer and the carrier blocking layer. A predetermined specific region is provided in the carrier blocking layer and extending from an interface between the carrier blocking layer and the light-emitting layer region and wherein a maximum value of a concentration of an impurity of the second conductivity type in the predetermined specific region is higher than 5×10.sup.19 cm.sup.−3.
LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING LIGHT-EMITTING ELEMENT
A nitride-based semiconductor light-emitting element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type; a carrier blocking layer of the second conductivity type, provided on a surface of the second semiconductor layer closer to the first semiconductor layer; and a light-emitting layer region having a light-emitting layer, provided between the first semiconductor layer and the carrier blocking layer. A predetermined specific region is provided in the carrier blocking layer and extending from an interface between the carrier blocking layer and the light-emitting layer region and wherein a maximum value of a concentration of an impurity of the second conductivity type in the predetermined specific region is higher than 5×10.sup.19 cm.sup.−3.
Light Emitting Diode and Fabrication Method Thereof
A light-emitting diode includes a material structure of barrier in the light-emitting well region to improve restriction capacity of electron holes, improving light-emitting efficiency of the LED chip under high temperature. The LED structure includes a Type I semiconductor layer, a Type II semiconductor layer and an active layer between the both, wherein, the active layer is a multi-quantum well structure alternatively composed of well layers and barrier layers, in which, the first barrier layer is a first AlGaN gradient layer in which aluminum components gradually increase in the direction from the Type I semiconductor layer to the quantum well, and the barrier layer at the middle of well layers is an AlGaN/GaN/AlGaN multi-layer barrier layer, and the last barrier layer is a second AlGaN gradient layer in which aluminum components gradually decrease in the direction from the quantum well to the Type II semiconductor layer.
LIGHT-EMITTING DEVICE AND LIGHTING SYSTEM COMPRISING SAME
Embodiments relate to a light emitting device, a light emitting device package, and a lighting system comprising the same. The light emitting device according to embodiments may comprise: a first conductivity-type semiconductor layer; an active layer on the first conductivity-type semiconductor layer; an electron blocking layer on the active layer; and a second conductivity-type semiconductor layer on the electron blocking layer. The electron blocking layer may comprise an In.sub.xAl.sub.yGa.sub.1-x-yN based superlattice layer (wherein 0≦x≦1, 0≦y≦1).
LIGHT-EMITTING DIODE (LED), LED PACKAGE AND APPARATUS INCLUDING THE SAME
A light-emitting diode (LED) package includes a light-emitting structure, an optical wavelength conversion layer on the light-emitting structure, and an optical filter layer on the optical wavelength conversion layer. The light-emitting structure includes a first-conductivity-type semiconductor layer, an active layer on the first-conductivity-type semiconductor layer, and a second-conductivity-type semiconductor layer on the active layer, and emits first light having a first peak wavelength. The optical wavelength conversion layer absorbs the first light emitted from the light-emitting structure and emits second light having a second peak wavelength different from the first peak wavelength. The optical filter layer reflects the first light emitted from the light-emitting structure and transmits the second light emitted from the optical wavelength conversion layer.
SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT
The semiconductor light-emitting element includes an n-type semiconductor layer; an active layer on the n-type semiconductor layer; a p-type semiconductor layer on the active layer; a p-side contact electrode in contact with the p-type semiconductor layer; a p-side current diffusion layer on the p-side contact electrode; an n-side contact electrode in contact with the n-type semiconductor layer; and an n-side current diffusion layer that includes a first current diffusion layer on the n-side contact electrode, and a second current diffusion layer on the first current diffusion layer, and including a TiN layer. A height difference between upper surfaces of the p-side contact electrode and the first current diffusion layer is 100 nm or smaller; and a height difference between upper surfaces of the p-side current diffusion layer and the second current diffusion layer is 100 nm or smaller.