A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A group-III-nitride structure and a manufacturing method thereof are provided. In the manufacturing method, one or more grooves are formed by etching a first group-III-nitride epitaxial layer with a patterned first mask layer as a mask; then a second mask layer is formed at least on one or more bottom walls of the one or more grooves, and a first epitaxial growth is performed on the first group-III-nitride epitaxial layer to laterally grow and form a second group-III-nitride epitaxial layer with the second mask layer as a mask, where the one or more grooves are filled with the second group III-nitride epitaxial layer; a second epitaxial growth is then performed on the second group-III-nitride epitaxial layer to grow and form a third group-III-nitride epitaxial layer on the second group-III-nitride epitaxial layer and the patterned first mask layer.

In various embodiments, the present disclosure includes a nitrogen-polar (N-polar) nanowire that includes an indium gallium nitride (InGaN) quantum well formed by selective area growth. It is noted that the N-polar nanowire is operable for emitting light.

A light emitting element includes a semiconductor core having at least a partial region extending in a direction and including a first end, a second end, and a main body part between the first end and the second end; a first electrode layer surrounding the second end of the semiconductor core; a second electrode layer surrounding at least the first end of the semiconductor core and spaced apart from the first electrode layer; and an insulating layer surrounding the semiconductor core, the first electrode layer and the second electrode layer. The second end of the semiconductor core has a diameter smaller than a diameter of the main body part.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

A method for porosifying a III-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first III-nitride material, having a charge carrier density greater than 5×10.sup.17 cm.sup.−3, beneath a surface layer of a second III-nitride material, having a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first III-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.

A display device may include pixels disposed on a substrate. Each of the pixels may include a first electrode, a second electrode spaced apart from the first electrode and enclosing a perimeter of the first electrode, light emitting elements disposed between the first electrode and the second electrode, and each including a first end and a second end, a third electrode overlapping the first electrode and the first end of each of the light emitting elements in a plan view, and electrically contacting the first electrode and the first end of each of the light emitting elements, and a fourth electrode overlapping the second electrode and the second end of each of the light emitting elements in a plan view, and electrically contacting the second electrode and the second end of each of the light emitting elements. The light emitting elements may be radially disposed around the first electrode.

The present disclosure describes epitaxial oxide field effect transistors (FETs). In some embodiments, a FET comprises: a substrate comprising an oxide material; an epitaxial semiconductor layer on the substrate; a gate layer on the epitaxial semiconductor layer; and electrical contacts. In some cases, the epitaxial semiconductor layer can comprise a superlattice comprising a first and a second set of layers comprising oxide materials with a first and second bandgap. The gate layer can comprise an oxide material with a third bandgap, wherein the third bandgap is wider than the first bandgap. In some cases, the epitaxial semiconductor layer can comprise a second oxide material with a first bandgap, wherein the second oxide material comprises single crystal A.sub.xB.sub.1-xO.sub.n, wherein 0<x<1.0, wherein A is Al and/or Ga, wherein B is Mg, Ni, a rare earth, Er, Gd, Ir, Bi, or Li.