A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

A ceramic green sheet including a plurality of substrate forming regions. A barcode or a two-dimensional code is drawn in a portion of the ceramic green sheet. The barcode or the two-dimensional code is obtained by encoding one or more of the following information. Information relating to raw materials used when the ceramic green sheet is produced, information relating to molding conditions of the ceramic green sheet, information relating to a release agent used when a plurality of the ceramic green sheets are stacked, or a serial number.

Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure. Also, a top surface of the molding layer, a top surface of the conductive post, and a top surface of the first adhesive layer may be coplanar.

An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

A display device includes: a display panel and a circuit board. The circuit board includes a base layer, a circuit pattern disposed on the base layer and electrically connected to the display panel, an alignment pattern disposed on the base layer and including the same material as the circuit pattern, a first cover layer disposed on the base layer, covering the circuit pattern, and provided with a first opening defined therethrough to expose the alignment pattern, and a second cover layer disposed on the first cover layer, provided with a second opening defined therethrough and overlapping the first opening, and including a barcode pattern defined on a surface of the second cover layer opposite to the first cover layer. The first cover layer overlapping the second opening is exposed through the second opening without being covered by the second cover layer.

The present invention aims to provide a shield package having a highly distinctive patterned portion formed on a surface of a shield layer. The shield package of the present invention includes a package in which an electronic component is sealed with a sealing material, and a shield layer covering the package, wherein a surface of the shield layer includes a patterned portion and a non-patterned portion other than the patterned portion, and a ratio of Sal (autocorrelation length) of the non-patterned portion to Sal of the patterned portion is as follows: (Sal of non-patterned portion)/(Sal of patterned portion)>4.0.

A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

A workpiece management method includes a frame unit forming step of forming a frame unit with a workpiece supported in an opening of an annular frame via a resin sheet, a printing step of, after performing the frame unit forming step, printing identification information of the workpiece on the resin sheet in an area between an outer periphery of the workpiece and an inner periphery of the annular frame, a processing step of processing the workpiece by a processing machine, a separation step of separating the processed workpiece from the resin sheet, and a storage step of storing the resin sheet from which the workpiece has been separated. A sheet cutting machine suitable for use in the workpiece management method is also disclosed.

Information regarding a semiconductor package is written on a stiffener and not on an upper surface of a semiconductor chip. The stiffener is positioned outside an outer edge of the semiconductor chip and inside an outer edge of a package base material. Further, a thermally conductive material having fluidity is disposed between the upper surface of the semiconductor chip and a radiator. Therefore, the semiconductor chip provides high cooling performance.

A marking method for applying a unique identification to each individual solar cell stack of a semiconductor wafer, at least comprising the steps: Providing a semiconductor wafer having an upper side and an underside, which comprises a Ge substrate forming the underside; and generating an identification with a unique topography by means of laser ablation, using a first laser, on a surface area of the underside of each solar cell stack of the semiconductor wafer, the surface area being formed in each case by the Ge substrate or by an insulating layer covering the Ge substrate.