A semiconductor device includes: a semiconductor wafer with a chip region and an edge region and with an identification mark formed on one surface of the semiconductor wafer in the edge region; conductive connectors formed on the one surface of the semiconductor wafer in the chip region; and dummy conductive connectors formed on the one surface of the semiconductor wafer in the edge region, wherein the dummy conductive connectors do not overlap with the identification mark.

A semiconductor package includes an encapsulation layer encapsulating at least one semiconductor chip, and a redistribution level layer disposed on the encapsulation layer. The redistribution level layer includes a redistribution layer and a redistribution insulating layer insulating the redistribution layer, a laser mark area is disposed on the redistribution layer and the redistribution insulating layer, and the redistribution insulating layer of the laser mark area comprises a plurality of mesh-type redistribution insulating patterns arranged apart from each other on a plane and surrounded by the redistribution layer. The redistribution level layer includes a laser mark insulating layer located on the redistribution layer and the redistribution insulating layer, wherein the laser mark insulating layer includes a laser mark exposing the redistribution layer and the mesh-type redistribution insulating patterns in the laser mark area.

A semiconductor package is provided. The semiconductor package includes: a first redistribution substrate; a semiconductor chip provided on the first redistribution substrate; a molding layer provided on the first redistribution substrate and the semiconductor chip; and a second redistribution substrate provided on the molding layer. The second redistribution substrate includes: redistribution patterns spaced apart from one another; a first dummy conductive pattern spaced apart from the redistribution patterns; an insulating layer provided on the first dummy conductive pattern; and a marking metal layer provided on the insulating layer and spaced apart from the first dummy conductive pattern. Sidewalls of the marking metal layer overlap the first dummy conductive pattern along a vertical direction perpendicular to an upper surface of the first redistribution substrate.

A photovoltaic cell is provided, including a substrate; a marked region on a surface of the substrate, configured to mark product information of the photovoltaic cell; a first texture structure in the marked region on the surface of the substrate, including at least one first protrusion structure and at least one second protrusion structure, a respective first protrusion structure of the at least one first protrusion structure has a recessed top surface recessing toward a bottom surface of the respective first protrusion structure, and a respective second protrusion structure of the at least one second protrusion structure includes a pyramid structure; and a second texture structure disposed on a part of the surface of the substrate outside the marked region, where the second texture structure includes at least one third protrusion structure, and a respective third protrusion structure of the at least one third protrusion structure includes a pyramid structure.

An electronic apparatus includes: a circuit board; a driving chip mounted on the circuit board; a shield-can including a top surface and a side surface extending in a direction from the top surface to the circuit board, wherein the top surface covers the driving chip; and a first film disposed on the shield-can and including a first opening that exposes a part of the top surface of the shield-can.

A system includes a separation tool that separates a carrier wafer to form a plurality of chiplet carriers. The carrier wafer having sheets of thin film material attached. A sensor and processor of the system determine an orientation of the portions of the sheets of thin film material relative to the chiplets to determine a mapping therebetween. A fluid carrier of the system places the chiplet carriers on an assembly surface in a disordered pattern. The system includes a micro assembler that arranges the chiplet carriers from the disordered pattern to a predetermined pattern based on the mapping. A carrier of the system transfers the portions of the thin film material from the chiplet carriers to a target substrate.

A system for performing a direct transfer of a semiconductor device die includes a first conveyance mechanism to convey a first substrate, and a second conveyance mechanism to convey a second substrate with respect to the first substrate. The first substrate includes a first side and a second side, and the semiconductor device die is disposed on the first side of the first substrate. The second conveyance mechanism includes a first portion and a second portion to clamp the second substrate adjacent to a first side of the first substrate. The first portion of the second conveyance mechanism has a concave shape and the second portion of the second conveyance mechanism has a convex counter shape corresponding to the concave shape of the first portion. The system also includes a transfer mechanism disposed adjacent to the first conveyance mechanism to effectuate the direct transfer.

A method includes loading a wafer tape into a first frame, the wafer tape having a first side and a second side, a first semiconductor device die being disposed on the first side of the wafer tape. A substrate is loaded into a second frame, the substrate including a second semiconductor device die onto which the first semiconductor device die is to be transferred. A needle is oriented to a position adjacent to the second side of the wafer tape, the needle extending in a direction toward the wafer tape, and a needle actuator connected to the needle is activated to move the needle to a die transfer position at which the needle contacts the second side of the wafer tape to press the first semiconductor device die into contact with the second semiconductor device die.

A system includes a separation tool that separates a carrier wafer to form a plurality of chiplet carriers. The carrier wafer having sheets of thin film material attached. A sensor and processor of the system determine an orientation of the portions of the sheets of thin film material relative to the chiplets to determine a mapping therebetween. A fluid carrier of the system places the chiplet carriers on an assembly surface in a disordered pattern. The system includes a micro assembler that arranges the chiplet carriers from the disordered pattern to a predetermined pattern based on the mapping. A carrier of the system transfers the portions of the thin film material from the chiplet carriers to a target substrate.

An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.