A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

An electronic semiconductor component with a housing structure and a cavity introduced into the housing structure is specified. The cavity comprises a base surface. Furthermore, the electronic semiconductor component comprises an auxiliary layer arranged on the base surface of the cavity and a marking penetrating the auxiliary layer at least as far as the base surface of the cavity. The marking comprises an optical contrast that depends on both an optical property of the housing structure and an optical property of the auxiliary layer. Furthermore, a method for producing an electronic semiconductor component is given.

A method of dampening a force applied to an electrically-actuatable element during a transfer of the electrically-actuatable element from a first side of a first substrate to a second substrate. The method includes positioning a needle adjacent a second side of the first substrate opposite the first side of the first substrate. The needle is moved via a needle actuator to a position at which the needle presses on the second side of the first substrate to press the electrically-actuatable element into contact with the second substrate disposed adjacent the first side of the first substrate. A force applied to the electrically-actuatable element is dampened when the needle presses the electrically-actuatable element into contact with the second substrate.

A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

According to one embodiment, a display device includes a display panel including a first substrate, and a wiring board mounted on a mounting portion of the first substrate. The display panel includes a first terminal and a second terminal located in the mounting portion, a first alignment mark located in the mounting portion and located between the first terminal and the second terminal, a first wiring line connected to the first terminal, and a second wiring line connected to the second terminal. The wiring board includes a first connection wiring line connected to the first terminal, a second connection wiring line connected to the second terminal, and a second alignment mark located between the first connection wiring line and the second connection wiring line.

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.

A semiconductor chip includes: a semiconductor substrate having driver circuitry configured to drive an array of electronic devices; a metal layer above the semiconductor substrate, the metal layer having an array of contacts electrically connected to the driver circuitry and configured to provide an electrical connection between the semiconductor chip and the array of electronic devices; and a plurality of structures formed in the metal layer and/or in a layer between the metal layer and the semiconductor substrate, the plurality of structures being visually unobstructed at a side of the metal layer which faces away from the semiconductor substrate. Each structure of the plurality of structures is physically encoded with a pattern that corresponds to a location of an individual pair of contacts within the array of contacts or a location of a group of adjacent pairs of contacts within the array of contacts.

Sheets of a thin film material are attached to a carrier wafer. The carrier wafer and the attached sheets of thin film material are separated to form chiplet carriers. Each chiplet carrier includes a portion of the sheets of thin film material attached to a portion of the carrier wafer. The chiplet carriers are placed on an assembly surface in a random pattern. The chiplet carriers are arranged from the random pattern to a predetermined pattern, and the portions of the thin film material are transferred from the chiplet carriers to a target substrate.

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.