A method of manufacturing a semiconductor chip includes preparing a semiconductor substrate having an active surface on which a device layer is provided and an inactive surface opposite to the active surface, the device layer having a integrated circuit (IC) areas and a cut area provided between adjacent IC areas; forming anti-collision recesses in regions of the cut area that are adjacent to corners of the IC areas, each of the anti-collision recesses having rounded internal sidewalls, each of the rounded internal sidewalls corresponding to a respective corner of the adjacent corners; forming a modified portion in the semiconductor substrate by irradiating a cut line of the cut area with a laser; polishing the inactive surface of the semiconductor substrate, wherein cracks propagate from the modified portion in a vertical direction of the semiconductor substrate; and separating the IC areas from each other along the cracks to form semiconductor chips.

The present disclosure illustrates a display panel manufacturing method including steps: disposing an alignment mark on a display panel; using an invisible-light identifier device to identify the alignment mark; and, processing the display panel according to the identified alignment mark. The invisible-light identifier device is configured to identify invisible light having wavelength longer than visible light.

Provided is a film for application to a 3D sample, the film including a photoresist layer that has alignment or direction marks thereon. After the fine pattern of the photoresist layer or coat is exposed, the photoresist layer is applied to a desired position of the 3D sample by aligning the alignment or direction marks of the film with alignment or direction marks on the 3D sample. This allows for transfer of an appropriate fine pattern. Part or all of the thickness or area of the photoresist layer is developed to form projections or depressions in the photoresist layer before the film is applied to the 3D sample.

A display substrate has a display area and a peripheral area. The display substrate includes a base, a first insulating layer disposed above the base, a first alignment pattern disposed in the peripheral area on a surface of the first insulating layer facing away from the base, and a second alignment pattern disposed in the peripheral area at a side of the first insulating layer away from the base. An orthographic projection of the second alignment pattern on the base and an orthographic projection of the first alignment pattern on the base have a non-overlapping region therebetween, and the second alignment pattern is in contact with the first insulating layer in the non-overlapping region. Adhesion between the second alignment pattern and the first insulating layer is greater than adhesion between the second alignment pattern and the first alignment pattern.

Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.

A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

An overlay mark includes a first, a second, a third, and a fourth component. The first component is located in a first region of the first overlay mark and includes a plurality of gratings that extend in a first direction. The second component is located in a second region of the first overlay mark and includes a plurality of gratings that extend in the first direction. The third component is located in a third region of the first overlay mark and includes a plurality of gratings that extend in a second direction different from the first direction. The fourth component is located in a fourth region of the first overlay mark and includes a plurality of gratings that extend in the second direction. The first region is aligned with the second region. The third region is aligned with the fourth region.

One or more semiconductor dice are arranged on a substrate. The semiconductor die or dice have a first surface adjacent the substrate and a second surface facing away from the substrate. Laser-induced forward transfer (LIFT) processing is applied to the semiconductor die or dice to form fiducial markers on the second surface of the semiconductor die or dice. Laser direct structuring (LDS) material is molded onto the substrate. The fiducial markers on the second surface of the semiconductor die or dice are optically detectable at the surface of the LDS material. Laser beam processing is applied to the molded LDS material at spatial positions located as a function of the optically detected fiducial markers to provide electrically conductive formations for the semiconductor die or dice.

A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.

A semiconductor unit includes: a semiconductor substrate; a first groove provided in the semiconductor substrate, having a first width W1 and extending in a first direction; and a second groove provided in the semiconductor substrate in communication with the first groove, having a second width W2 different from the first width, and extending in a second direction that intersects the first direction, in which one of the first groove and the second groove is used for alignment.