The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.

A metrology system may include an imaging sub-system to image a metrology target buried in a sample, where the sample is formed from bonded first and second substrates with a metrology target at the interface. The metrology system may further include an illumination sub-system with an illumination field stop and an illumination pupil, where the illumination field stop includes an aperture to provide that a projected size of the field-stop aperture on a measurement plane corresponding to the metrology target matches a field of view of the detector at the measurement plane, and where the illumination pupil includes a central obscuration to provide oblique illumination of the metrology target with angles greater than a cutoff angle selected to prevent illumination from the illumination source from reflecting off of the bottom surface of the sample and through the field of view of the detector at the measurement plane.

An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A semiconductor device includes a first lead, a second lead, a control element, an insulating element, and a driver element. The control element and insulating element are mounted on a first pad portion of the first lead, while the driver element on a second pad portion of the second lead. In plan view, the first pad portion has a first edge adjacent to the second pad portion in a first direction and extending in a second direction perpendicular to the first direction. The first edge has first and second ends opposite in the second direction. The second pad portion has a second edge adjacent to the first edge and extending in the second direction. The second edge has third and fourth ends opposite in the second direction. One of the third and fourth end is located between the first and second end in the second direction.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising <lmn>, wherein l.sup.2+m.sup.2+n.sup.2=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.

Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. The lithographic patterning system includes an actinic radiation source, a stage having a surface for supporting a substrate with a resist layer, and a prism with a first surface over the stage, where the first surface has a masked layer and is substantially parallel to the surface of the stage. The prism may have a second surface that is substantially parallel to the first surface. The first and second surfaces are flat surfaces. The prism is a monolithic prism-mask, where an optical path passes through the system and exits the first surface of the prism through the mask layer. The system may include a layer disposed between the mask and resist layers. The mask layer of the prism may pattern the resist layer without an isolated mask layer.