A method of fabricating radiation sensor dies includes forming a plurality of radiation-sensitive detector elements and a plurality of visible identifiers on at least some of the radiation-sensitive detector elements on a substrate, where each visible identifier is located in a different sub-region of the substrate containing a subset of the radiation-sensitive detector elements, and separating the sub-regions of the substrate from one another to provide a plurality of radiation sensor dies, where the visible identifier on each radiation sensor die uniquely identifies the radiation sensor die with respect to the other radiation sensor dies of the plurality of radiation sensor dies.

A semiconductor device includes a semiconductor chip and a metal plate. The semiconductor chip has first and second surfaces, four side surface, four corners, four sides. The four side surfaces connect the first surface and the second surface. Two of the four side surfaces contact each other at one of the four corners. The four side surfaces contact the second surface at the four sides. The first and second electrodes are provided at the first front side. The metal plate is connected to the second surface side of the semiconductor chip. The metal plate includes third and fourth surfaces, and a through-hole or a notch. The third surface is connected to the second surface of the semiconductor chip. The fourth surface is provided at a side opposite to the third surface. The through-hole or the notch extends through the metal plate from the fourth surface to the third surface.

Disclosed in the present specification are a substrate for transferring, with high reliability, a semiconductor light emitting element, and a method for manufacturing a display device by using same. Particularly, when a semiconductor light emitting element is self-assembled on an assembly substrate by using an electromagnetic field, an assembly groove in which a semiconductor light emitting element for alignment is assembled is formed in the assembly substrate. The semiconductor light emitting element for alignment, assembled in the assembly groove, is used for alignment in a step of being transferred to a final wiring substrate. Unlike conventional alignment keys, the semiconductor light emitting element for alignment reflects an alignment error of semiconductor light emitting elements that occurs during a transfer process after assembly. Therefore, when semiconductor light emitting elements are transferred to a wiring substrate on the basis of the semiconductor light emitting element for alignment, transfer accuracy can be improved.

A method of configuring a mark having a trench to be etched into a substrate, the method including: obtaining a relation between an extent of height variation across a surface of a probationary layer deposited on a probationary trench of a probationary depth and a thickness of the probationary layer; determining an extent of height variation across the surface of a layer deposited on the mark allowing a metrology system to determine a position of the mark; and configuring the mark by determining a depth of the trench based on the relation, the extent of height variation and the thickness of a process layer to be deposited on the mark.

The instant disclosure includes an alignment system. The alignment system includes a first set of alignment marks, a second set of alignment marks, and a third set of alignment marks. The first, second and third alignment marks correspondingly includes a plurality of segments separated into groups. Each of the group being symmetric to a respective other group. The third set of alignment marks are diagonal to the first set of alignment marks and the second set of alignment marks.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.

The present invention relates to a power module and a method for manufacturing same, in which an insulating spacer is disposed between two upper and lower substrates to thus efficiently dissipate the heat generated from a semiconductor chip mounted between the substrates, and prevent bending deformation due to heat. In addition, since the spacer made of an insulating material is integrated with the substrates by brazing bonding, the bonding strength is improved, thereby maintaining strong bonding even against vibration, etc.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.