Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate.

In one example, a method of manufacturing a semiconductor device includes providing a substrate having substrate terminals and providing a component having a first component terminal and a second component terminal adjacent to a first major side of the component. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first component terminal and a first substrate terminal and coupling the second clip to a second substrate terminal. The method includes encapsulating the component, portions of the substrate, and portions of the clip structure. the method includes removing a sacrificial portion of the clip connector while leaving a first portion of the clip connector attached to the first clip and leaving a second portion of the clip connector attached to the second clip. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant after the removing. Other examples and related structures are also disclosed herein.

A wafer manufacturing method for manufacturing a wafer from an ingot includes forming a peeling layer within the ingot by positioning a condensing point at a depth corresponding to the thickness of the wafer to be produced, and irradiating the ingot with a first laser beam, forming a character, a number, or a mark representing information regarding resistivity in or on the ingot by positioning a condensing point in a region in which devices are not to be formed and irradiating the ingot with a second laser beam, and dividing the ingot with the peeling layer as a starting point.

A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

Apparatus and methods for determining wafer characters are disclosed. In one example, an apparatus is disclosed. The apparatus includes: a processing tool configured to process a semiconductor wafer; a device configured to read an optical character disposed on the semiconductor wafer while the semiconductor wafer is located at the apparatus for wafer fabrication; and a controller configured to determine whether the optical character matches a predetermined character corresponding to the semiconductor wafer based on the optical character read in real-time at the apparatus.

Systems and processes for flexible and/or low volume product manufacture, including cost effective ways to manufacture low volume system level devices. In one aspect, this disclosure enables the manufacture of a plurality of System in Package (SiP) devices. In one aspect, the devices include one or more of an optical and electrical identifier, corresponding to substrates and/or product designs. The identifiers can be used in the assembly of the devices.

According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

A production method for a semiconductor element (10) includes: a semiconductor element forming step of forming the semiconductor element (10) including a dielectric film (3); a dicing region forming step of forming dicing regions (11) by removing the dielectric film (3) in partition regions that partition the semiconductor element (10); and a dicing step of dicing the dicing regions (11).