A method and device for the alignment of substrates that are to be bonded. The method includes detecting and storing positions of alignment mark pairs located on surfaces of the substrates, and aligning the substrates with respect to each other in accordance with the detected positions.

Embodiments of the present invention provide an electroplating apparatus for electroplating on a surface of a wafer, the electroplating apparatus comprising a plurality of electrodes, the plurality of electrodes forming electric fields on the surface of the wafer, wherein an independent electric field is formed in a designated area, the intensity of the independent electric field is independently controlled, when a notch of the wafer is positioned within the designated area, a total amount of power received by the notch within the designated area is reduced. Embodiments of the present invention also provide an electroplating method for electroplating on a surface of a wafer by using a plurality of electrodes, the method controlling the plurality of electrodes to form electric fields on the surface of the wafer, wherein an independent electric field is formed in a designated area, the intensity of the independent electric field is independently controlled, when a notch of the wafer is positioned within the designated area, a total amount of power received by the notch within the designated area is reduced. The electroplating apparatus and the electroplating method of the present invention control the electroplating height of the notch of the wafer by directly controlling the intensity of the electric field. Compared with a conventional control method which only changing the rotation speed of the wafer, the present invention is more accurate and reliable, the electroplating efficiency is also increased.

An object is to provide a SiC wafer in which a detection rate of an optical sensor can improved and a SiC wafer manufacturing method.

The method includes: a satin finishing process S141 of satin-finishing at least a back surface 22 of a SiC wafer 20; an etching process 21 of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure after the satin finishing process S141; and a mirror surface processing process S31 of mirror-processing a main surface 21 of the SiC wafer 20 after the etching process S21. Accordingly, it is possible to obtain a SiC wafer having the mirror-finished main surface 21 and the satin-finished back surface 22.

A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.

A semiconductor device is provided. The semiconductor device includes: a plurality of alignment dies, each including a diced first base substrate and at least one alignment mark on the diced first base substrate; a second base substrate; and a bonding film on the second base substrate. An alignment die of the plurality of alignment dies are attached on the bonding film on an alignment region of the second base substrate for aligning the second base substrate.

Systems for annealing a wafer are provided. A system includes a wafer stage, a laser beam generator, and a controller. The laser beam generator is configured to generate a laser beam. The controller is configured to control the laser beam generator according to information regarding layout of a first semiconductor die of the wafer, so as to project the laser beam with a first laser parameter onto the first semiconductor die of the wafer on the wafer stage along at least one annealing orbit. The controller is configured to arrange the annealing orbit to partially cover the first semiconductor die of the wafer and to uncover a plurality of second semiconductor dies of the wafer.

A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

A substrate transfer method includes: acquiring sensing information from a sensor by moving a substrate by a robot arm such that the substrate passes through a sensing region; calculating a center position of the substrate with respect to the robot arm based on the sensing information; detecting a marker indicating a reference direction of the substrate by the sensor by controlling the robot arm to rotate the substrate about the center position in a state where an edge of the substrate is located in the sensing region; calculating a direction of the substrate with respect to the robot arm based on a position of the marker; calculating a correction amount based on the center position and the direction of the substrate; and placing the substrate on the stage in the processing chamber such that the center position and the direction of the substrate are corrected according to the correction amount.

Embodiments of the present disclosure generally relate to an optically transparent substrate, comprising a major surface having a peripheral edge region with an orientation feature formed therein, and a texture formed on the peripheral edge region, the texture having an opacity that is greater than an opacity of the major surface.

The present invention provides an aluminum nitride wafer and a method for making the same. The method includes forming at least one alignment notch in or at least one flat alignment edge on a periphery of the aluminum nitride wafer. The alignment notch and the flat alignment edge can prevent the aluminum nitride wafer from being in a poor state during the semiconductor manufacturing process and makes it possible to position the aluminum nitride wafer precisely so that the fraction defective can be lowered. The aluminum nitride wafer of the present invention has advantages of effective insulation, efficient heat dissipation, and a high dielectric constant, and can be used in semiconductor manufacturing processes, electronic products, and semiconductor equipment.