Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.

The present disclosure provides a display device, including a substrate, a plurality of semiconductor light emitting devices arranged on the substrate, a first wiring electrode and a second wiring electrode extended from the semiconductor light emitting devices, respectively, to supply an electric signal to the semiconductor light emitting devices, a plurality of pair electrodes arranged on the substrate to generate an electric field when an electric current is supplied, and provided with first and second pair electrodes formed on an opposite side to the first and second wiring electrodes with respect to the semiconductor light emitting devices, and a dielectric layer formed to cover the pair electrodes, wherein the plurality of pair electrodes are arranged in parallel to each other along a direction.

The present disclosure provides a display device, including a substrate, a plurality of semiconductor light emitting devices arranged on the substrate, a first wiring electrode and a second wiring electrode extended from the semiconductor light emitting devices, respectively, to supply an electric signal to the semiconductor light emitting devices, a plurality of pair electrodes arranged on the substrate to generate an electric field when an electric current is supplied, and provided with first and second pair electrodes formed on an opposite side to the first and second wiring electrodes with respect to the semiconductor light emitting devices, and a dielectric layer formed to cover the pair electrodes, wherein the plurality of pair electrodes are arranged in parallel to each other along a direction.

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.

The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.