A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.

A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.

A method of pressing solder bumps using a pressing apparatus before testing a wafer, including loading the wafer into the pressing apparatus, where the wafer includes a number of chips, and the wafer is aligned with respect to a test head of the pressing apparatus. The test head includes a substrate which has pressing structures arranged across a surface of the substrate facing the wafer. The pressing structures contact the solder bumps, where the solder bumps include a first surface topology and the pressing structures include a pressing surface topology prior to the contact. The caused contact includes altering a shape of each of the plurality of solder bumps, such that the plurality of solder bumps then a second surface topology after the caused contact, and the second surface topology of the solder bumps matches the pressing surface topology after the caused contact.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive feature. The bumps are disposed on the first semiconductor die and are connected to the first conductive feature. The substrate includes a second conductive feature. The bumps are electrically connected to the second conductive feature. The first conductive feature, the bumps, and the second conductive feature are configured to form at least one ring structure.

An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive feature. The bumps are disposed on the first semiconductor die and are connected to the first conductive feature. The substrate includes a second conductive feature. The bumps are electrically connected to the second conductive feature. The first conductive feature, the bumps, and the second conductive feature are configured to form at least one ring structure.

A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.

A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.