A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.

A method for producing a power-electronics switching device and a power electronic switching device produced thereby. In the power-electronics switching device, a power semiconductor component is arranged on a first region of a conductor track of a substrate. An insulating film comprising a cutout is then provided, wherein an overlap region of the insulating film, which overlap region is adjacent to the cutout, is designed to cover an edge region of the power semiconductor component. This is followed by arranging the insulating film on the substrate, with the power semiconductor component arranged on it, in such a way that the power semiconductor component is covered on all sides of its edge region by the covering region of the insulating film, wherein a further section of the insulating film covers parts of one of the conductor tracks. Finally, the connecting device is arranged.

A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature.

A display device includes a substrate, conductive pads arranged on the substrate over a plurality of rows, and a drive circuit chip including bumps arranged over a plurality of rows to be electrically connected with the conductive pads, and the conductive pads arranged in a same row are arranged in parallel, and the bumps arranged in a same row are arranged in a zigzag form so as to be partially shifted.

A display device includes a substrate, conductive pads arranged on the substrate over a plurality of rows, and a drive circuit chip including bumps arranged over a plurality of rows to be electrically connected with the conductive pads, and the conductive pads arranged in a same row are arranged in parallel, and the bumps arranged in a same row are arranged in a zigzag form so as to be partially shifted.

A semiconductor package includes a substrate including bonding pads, semiconductor chips stacked on the substrate and each including a lower surface and an upper surface, and connection pads on the upper surface, connection films spaced apart from each other in a first direction, the connection films electrically connecting the connection pads and corresponding ones of the bonding pads to each other in a second direction intersecting the first direction, a mold covering the semiconductor chips and the connection films, and connection bumps being under the substrate, the connection bumps electrically connected to the bonding pads. Each of the connection films includes a flexible film covering at least two connection pads adjacent to each other in the first direction, among the connection pads, and conductive lines extending in the second direction on the flexible film, the conductive lines respectively connected to the at least two connection pads.