There is a problem that the reliability of insulation is lowered. A length L2 from a center P of a conductor layer 334 to a peripheral edge portion of an insulating member 333 is formed to be longer than a length L1 from the center P of the conductor layer 334 to a peripheral edge portion of a protruding portion 307a of a base member 307. In other words, a base end surface 308 of the peripheral edge portion of the protruding portion 307a is located on an inner side with respect to an insulating member end surface 336 of the peripheral edge portion of the insulating member 333. Further, the insulating member end surface 336 of the insulating member 333 and a conductor layer end surface 344 of the conductor layer form an end surface at the same position. Since the base end surface 308 of the peripheral edge portion of the protruding portion 307a is located on the inner side with respect to the insulating member end surface 336 of the peripheral edge portion of the insulating member 333 in this manner, an insulation distance can be secured.

Provided is a pressurized semiconductor package including a lead frame including a pad board and a first terminal, a semiconductor chip, pressurizing members stacked to pressurize the semiconductor chip, and a package housing. The semiconductor chip is physically pressurized by the pressurizing members and is electrically connected to improve durability of the semiconductor package and to simplify a manufacturing process.

Provided is a pressurized semiconductor package including a lead frame including a pad board and a first terminal, a semiconductor chip, pressurizing members stacked to pressurize the semiconductor chip, and a package housing. The semiconductor chip is physically pressurized by the pressurizing members and is electrically connected to improve durability of the semiconductor package and to simplify a manufacturing process.

A power semiconductor module comprises abase plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).

There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

This application is directed to a semiconductor system including a substrate, an electronic device, a plurality of compliant interconnects and a support structure. The substrate has a first surface and a plurality of first contacts formed on the first surface. The electronic device has a second surface facing the first surface of the substrate, and a plurality of second contacts formed on the second surface. The compliant interconnects are disposed between the first surface of the substrate and the second surface of the electronic device, and are configured to electrically couple the first contacts on the first surface of the substrate to the second contacts on the second surface of the electronic device. The support structure is coupled to the substrate and the electronic device, and extends beyond a footprint of the electronic device. The support structure is configured to mechanically couple the electronic device to the substrate.

This application is directed to a semiconductor system including a substrate, an electronic device, a plurality of compliant interconnects and a support structure. The substrate has a first surface and a plurality of first contacts formed on the first surface. The electronic device has a second surface facing the first surface of the substrate, and a plurality of second contacts formed on the second surface. The compliant interconnects are disposed between the first surface of the substrate and the second surface of the electronic device, and are configured to electrically couple the first contacts on the first surface of the substrate to the second contacts on the second surface of the electronic device. The support structure is coupled to the substrate and the electronic device, and extends beyond a footprint of the electronic device. The support structure is configured to mechanically couple the electronic device to the substrate.

A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

A power semiconductor module comprises a base plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).