Provided is a pressurized semiconductor package including a lead frame including a pad board and a first terminal, a semiconductor chip, pressurizing members stacked to pressurize the semiconductor chip, and a package housing. The semiconductor chip is physically pressurized by the pressurizing members and is electrically connected to improve durability of the semiconductor package and to simplify a manufacturing process.

Provided is a pressurized semiconductor package including a lead frame including a pad board and a first terminal, a semiconductor chip, pressurizing members stacked to pressurize the semiconductor chip, and a package housing. The semiconductor chip is physically pressurized by the pressurizing members and is electrically connected to improve durability of the semiconductor package and to simplify a manufacturing process.

A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features.

A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features.

The invention relates to a modular element (2) comprising a stratification of first and second electroconductive plates (PH2, PB2) which are separated by an intermediate dielectric layer (CD2) and at least one electronic power switching chip (CP1, CP2) which is implanted between the first and second plates, the chip having a upper face comprising a first power electrode and a switching control electrode and a lower face comprising a second power electrode, and the first and second power electrodes being in electrical continuity respectively with the first and second plates. According to the invention, the modular element comprises a plurality of openings (OG2, OA2, OB2, OC2, OD2) extending into the stratification from outer surfaces of the first and second plates and perpendicularly to said outer surfaces, the plurality of openings comprising at least one first opening (OG2) communicating with the switching control electrode and at least one second opening (OA2, OB2) passing through the entire stratification, the first and second openings each comprising a dielectric layer (DE2) and an electroconductive layer (CI2), and the electroconductive layer of the first opening being electrically connected to the switching control electrode.

The invention relates to a modular element (2) comprising a stratification of first and second electroconductive plates (PH2, PB2) which are separated by an intermediate dielectric layer (CD2) and at least one electronic power switching chip (CP1, CP2) which is implanted between the first and second plates, the chip having a upper face comprising a first power electrode and a switching control electrode and a lower face comprising a second power electrode, and the first and second power electrodes being in electrical continuity respectively with the first and second plates. According to the invention, the modular element comprises a plurality of openings (OG2, OA2, OB2, OC2, OD2) extending into the stratification from outer surfaces of the first and second plates and perpendicularly to said outer surfaces, the plurality of openings comprising at least one first opening (OG2) communicating with the switching control electrode and at least one second opening (OA2, OB2) passing through the entire stratification, the first and second openings each comprising a dielectric layer (DE2) and an electroconductive layer (CI2), and the electroconductive layer of the first opening being electrically connected to the switching control electrode.

A device for cooling a plurality of electrical components, each having a component cooling surface to be cooled, includes a first heat sink, a second heat sink, and a plurality of fasteners. The first heat sink has a first heat-sink cooling surface, and the second heat sink has a second heat-sink cooling surface. The first and second heat-sink cooling surfaces are positioned in a planar arrangement such that the first and second heat-sink cooling surfaces face each other. The first heat-sink cooling surface is configured to receive a first sub-set of the component cooling surfaces of the plurality of electrical components, and the second heat-sink cooling surface is configured to receive a second sub-set of the component cooling surfaces. The fasteners are configured to fasten the first and second heat-sink cooling surfaces to the corresponding component cooling surfaces of the plurality of electrical components to be applied.

A device for cooling a plurality of electrical components, each having a component cooling surface to be cooled, includes a first heat sink, a second heat sink, and a plurality of fasteners. The first heat sink has a first heat-sink cooling surface, and the second heat sink has a second heat-sink cooling surface. The first and second heat-sink cooling surfaces are positioned in a planar arrangement such that the first and second heat-sink cooling surfaces face each other. The first heat-sink cooling surface is configured to receive a first sub-set of the component cooling surfaces of the plurality of electrical components, and the second heat-sink cooling surface is configured to receive a second sub-set of the component cooling surfaces. The fasteners are configured to fasten the first and second heat-sink cooling surfaces to the corresponding component cooling surfaces of the plurality of electrical components to be applied.