An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a modified extracted die, which includes one or more extended bond pads, a package comprising a base and a lid, and a plurality of new bond wires. The modified extracted die is placed into a cavity of the base. After the modified extracted die is placed into the cavity, the plurality of new bond wires are bonded between the one or more extended bond pads of the modified extracted die and package leads of the package base or downbonds. After bonding the plurality of new bond wires, the lid is sealed to the base.

A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.

A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

A substrate bonding method includes a plasma processing step of processing a bonding surface of each of the substrates with a rare gas plasma which is a plasma of a rare gas, processing the bonding surface of each of the substrates processed with the rare gas plasma with a hydrogen plasma which is a plasma of hydrogen, and processing the bonding surface of each of the substrates processed with the hydrogen plasma with a nitrogen plasma which is a plasma of nitrogen and a substrate bonding step of bonding two substrates by bringing the bonding surfaces of the two substrates into contact with each other such that copper pads of the two substrates face each other and insulating films of the two substrates face each other after the plasma processing step.

Provided is an apparatus for packing a semiconductor, and more particularly, to an apparatus for packing a semiconductor, which packages a semiconductor element in a wafer level packaging manner. The apparatus for packaging the semiconductor includes a loading unit having a space in which a process of disposing a mask member on a wafer including a plurality of semiconductor elements is performed, a deposition unit having a space, in which a process of transferring the wafer and the mask member from the loading unit to form a conductive pattern layer on the wafer is performed, and connected to the loading unit, and an unloading unit having a space, in which a process of transferring the wafer and the mask member from the deposition unit to separate the mask member from the wafer is performed, and connected to the deposition unit.