H01L2224/75

BONDING HEAD, DIE BONDING APPARATUS INCLUDING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME

A bonding head for a die bonding apparatus and a die bonding apparatus including the bonding head, the bonding head including a head body; a thermal pressurizer mounted on a lower surface of the head body, the thermal pressurizer being configured to hold and heat at least one die and including a heater having a first heating surface that faces a held surface of the die; and a thermal compensator at an outer region of the die, the thermal compensator extending downwardly from the lower surface of the head body and including at least one thermal compensating block having a second heating surface that emits heat from a heating source therein and that faces a side surface of the die held on the thermal pressurizer.

CHIP CARRYING STRUCTURE HAVING CHIP-SUCTION FUNCTION
20210134613 · 2021-05-06 ·

A chip carrying structure having chip-suction function is provided. The chip carrying structure includes a non-circuit substrate and a plurality of micro heaters. The non-circuit substrate has a plurality of openings and a plurality of air extraction channels respectively communicated with the openings. The micro heaters are disposed on the non-circuit substrate and carried by the non-circuit substrate. Each of the openings of the non-circuit substrate contacts and suctions one of a plurality of chips, and no adhesive layer is disposed between the non-circuit substrate and the chip. When air is exhausted from the air extraction channels, the openings of the non-circuit substrate can be used to respectively suck the chips, so that the chips can be attached to the non-circuit substrate, and the micro heater can heat a solder ball that is contacted by the chip.

Integrated circuit controlled ejection system (ICCES) for massively parallel integrated circuit assembly (MPICA)
10964561 · 2021-03-30 · ·

Methods, systems, and apparatuses are described for integrated circuit controlled ejection system (ICCES) for massively parallel integrated circuit assembly (MPICA). A unique Integrated Circuit (IC) die ejection head assembly system is described, which utilizes Three-Dimensional (3D) printing to achieve very high resolution manufacturing to meet the precision tolerances required for very small IC die sizes.

Pressure sintering procedure in which power semiconductor components with a substrate are connected to each other via a sintered connection

The invention provides a pressure sintering method including: a) providing a sintered component arrangement with a workpiece carrier having recesses, with a substrate resting on a main surface of the workpiece carrier, wherein a sintering material to be sintered is arranged between the power semiconductor components and the substrate, a first power semiconductor component and a first region of the substrate arranged above the workpiece carrier in the normal direction of the first main side of the insulation layer flush with a first recess of the workpiece carrier, and a second power semiconductor component and a second region of the substrate are arranged above the workpiece carrier in the normal direction of the first main side of the insulation layer flush with a second recess of the workpiece carrier and a step of b) pressurizing the power semiconductor components and applying a temperature treatment.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
20210090903 · 2021-03-25 ·

A method for manufacturing a semiconductor device includes forming a bonding layer on a back-surface of a semiconductor element, mounting the semiconductor element on a base member, and bonding the semiconductor element to the base member by pressing the semiconductor element on the base member. The bonding layer includes tin. The base member includes a plating layer that includes silver and tin. The base member is heated at a prescribed temperature. The semiconductor element is placed on the base member so that the bonding layer contacts the plating layer on the base member.

TRANSFER HEAD AND METHOD OF MANUFACTURING MICRO LED DISPLAY USING SAME
20210043797 · 2021-02-11 ·

The present invention relates to a transfer head and a method of manufacturing a micro LED display using the same. In particular, the present invention relates to a transfer head and a method of manufacturing a micro LED display using the same, the transfer head mounting normal micro LEDs on a display substrate without performing a complicated process of sorting out defective micro LEDs from the micro LEDs mounted on the display substrate and replacing the defective micro LEDs with normal micro LEDs.

PRESSURIZING DEVICE AND PRESSURIZING METHOD
20210028018 · 2021-01-28 · ·

A pressurizing device includes: a mounting base; an upper mold which pressurizes the target object mounted on the mounting base from above; a heating lower mold which is a lower mold heated in advance by a heater, and which heats the target object under pressure by sandwiching the mounting base with the upper mold; a cooling lower mold which is a lower mold cooled in advance by a cooler, and which cools the target object under pressure by sandwiching the mounting base with the upper mold; and a control device which switches the lower mold that contributes to the pressurization of the target object to the heating lower mold or the cooling lower mold in accordance with the status of progress of the pressurization process for the target object.

Bonding apparatus and method for detecting height of bonding target
10816322 · 2020-10-27 · ·

A bonding apparatus having an optical system, an imaging element for acquiring an image formed by the optical system as a picture, an illumination unit for illuminating an electronic component, and a control part for processing the image acquired by the imaging element, the control part illuminating the electronic component through a first inclined optical path inclined with respect to the optical axis of a first portion of the optical system facing the electronic component and acquiring a first image, illuminating the electronic component through a second inclined optical path inclined toward the opposite side from the first inclined optical path with respect to the optical axis and acquiring a second image of the electronic component as a subject, and calculating an amount of variation from a reference height of the electronic component on the basis of the positional offset amount between the first image and the second image.

BONDED NANOFLUIDIC DEVICE CHIP STACKS

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

BONDED NANOFLUIDIC DEVICE CHIP STACKS

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.