An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer.

Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A semiconductor device includes a first semiconductor component including a first semiconductor substrate and a first wiring structure, and a second semiconductor component including a second semiconductor substrate and a second wiring structure. A first surface of the first semiconductor component and a second surface of the second semiconductor component are bonded together. Assuming that regions having circumferences respectively corresponding to shapes obtained by vertically projecting the first surface, the second surface, the first wiring structure, and the second wiring structure on a virtual plane are first to fourth regions, respectively, an area of the first region is smaller than an area of the second region, the entire circumference of the first region is included in the second region, an area of the fourth region is smaller than an area of the third region, and the entire circumference of the fourth region is included in the third region.

A semiconductor device includes a first semiconductor component including a first semiconductor substrate and a first wiring structure, and a second semiconductor component including a second semiconductor substrate and a second wiring structure. A first surface of the first semiconductor component and a second surface of the second semiconductor component are bonded together. Assuming that regions having circumferences respectively corresponding to shapes obtained by vertically projecting the first surface, the second surface, the first wiring structure, and the second wiring structure on a virtual plane are first to fourth regions, respectively, an area of the first region is smaller than an area of the second region, the entire circumference of the first region is included in the second region, an area of the fourth region is smaller than an area of the third region, and the entire circumference of the fourth region is included in the third region.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.