Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having top-side connection pads, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die coupled with the first side of the substrate, a plurality of connection pads coupled with the first side of the substrate, and a plurality of interconnect structures coupled with the plurality of connection pads. Other embodiments may be described and/or claimed.

A method of forming a semiconductor wafer is provided. The method includes dicing wafers into dies, testing the dies for known good dies, and bonding known good dies to a carrier wafer to form a top KGD wafer. The method also includes filling gaps between top dies to form a top gap-fill layer around and above each of the top dies, and bonding the top dies with a dummy silicon wafer. The method also includes bonding known good dies to carrier wafers to form one or more core KGD wafers, as well as filling gaps between the core dies to form a core gap-fill layer around each of the core dies. The method then includes bonding the one or more core KGD wafers to the top KGD wafer to form a KGD wafer stack.

A stacking structure including a first die and a second die stacked the first die is provided. The first die includes a first substrate and a first bonding structure located over the first substrate. The second die includes a second substrate and a second bonding structure located over the second substrate. The first and second dies are bonded through the bonded first and second bonding structures. The bonded first and second bonding structures include fused bonding pads having homogeneous core pads and locking patterns surrounding the homogeneous core pads.

A method of forming a bonded wafer, where the method includes receiving a first wafer including a first surface characteristic and a second wafer including a second surface characteristic; based on the first surface characteristic, performing a first location specific processing on the first wafer to obtain a first surface-to-be-bonded including a third surface characteristic; and bonding the first surface-to-be-bonded of the first wafer with the second wafer.