Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

A core material has a core; a solder layer provided outside the core and being a solder alloy containing Sn and at least any one element of Ag, Cu, Sb, Ni, Co, Ge, Ga, Fe, Al, In, Cd, Zn, Pb, Au, P, S, Si, Ti, Mg, Pd, and Pt; and a Sn layer provided outside the solder layer. The solder layer has a thickness of 1 μm or more on one side. The Sn layer has a thickness of 0.1 μm or more on one side. A thickness of the Sn layer is 0.215% or more and 36% or less of the thickness of the solder layer.

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

A method for interconnecting two conductors includes creating a first nickel layer on a first conductor of an electrical component, producing a first non-gold protective layer on the first nickel layer, the first non-gold protective layer being configured to prevent the first nickel layer from oxidizing, creating a second nickel layer on a second conductor, producing a second non-gold protective layer on the second nickel layer, the second non-gold protective layer being configured to prevent the second nickel layer from oxidizing, and interconnecting the first and second nickel layers using a solder layer that interfaces with the first and second nickel layers between the first and second conductors.

A method for interconnecting two conductors includes creating a first nickel layer on a first conductor of an electrical component, producing a first non-gold protective layer on the first nickel layer, the first non-gold protective layer being configured to prevent the first nickel layer from oxidizing, creating a second nickel layer on a second conductor, producing a second non-gold protective layer on the second nickel layer, the second non-gold protective layer being configured to prevent the second nickel layer from oxidizing, and interconnecting the first and second nickel layers using a solder layer that interfaces with the first and second nickel layers between the first and second conductors.

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 μm and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.