A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

A lead-free solder alloy having a low melting temperature and low yield strength is disclosed. The solder alloy includes 5.0-20.0 wt. % of indium (In), 1.0-5.0 wt. % of silver (Ag), 0.25-2.0 wt. % of copper (Cu), 0.1-0.5 wt. % of zinc (Zn), and a remainder of tin (Sn). In implementations, a sulfur compound may be included in a concentration of 100 ppm to 500 ppm in the alloy to prevent oxidation of zinc and indium on the surface of the alloy. The solder alloy is particularly useful for but not limited to solder on pad applications in first level interconnect semiconductor device packaging.

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.

A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.

A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.

Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.