An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

Described herein is a method and a power semiconductor device produced by the method. The method includes: forming a structured metallization layer above a semiconductor substrate; forming a protective layer on the structured metallization layer; forming a first passivation over the structured metallization layer with the protective layer interposed between the first passivation and the structured metallization layer; structuring the first passivation to expose one or more regions of the protective layer; removing the one or more exposed regions of the protective layer to expose one or more parts of the structured metallization layer; and after structuring the first passivation and removing the one or more exposed regions of the protective layer, forming a second passivation on the first passivation and electroless plating the one or more exposed parts of the structured metallization layer.

A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.

A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal molded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal molded bodies, and applying the metal molded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the molded body.

The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal molded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal molded bodies, and applying the metal molded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the molded body.

Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base.