Patent classifications
H01L2924/01045
PALLADIUM-COATED COPPER BONDING WIRE, MANUFACTURING METHOD OF PALLADIUM-COATED COPPER BONDING WIRE, SEMICONDUCTOR DEVICE USING THE SAME, AND MANUFACTURING METHOD THEREOF
A palladium-coated copper bonding wire includes: a core material containing copper as a main component; and a palladium layer on the core material, in which a concentration of palladium relative to the entire wire is 1.0 mass % or more and 4.0 mass % or less, and a work hardening coefficient in an amount of change of an elongation rate 2% or more and a maximum elongation rate εmax % or less of the wire, is 0.20 or less.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
Pillar bump with noble metal seed layer for advanced heterogeneous integration
A pillar bump structure, and a method for forming the same includes forming, on a semiconductor substrate, a blanket liner followed by a seed layer including a noble metal. A first photoresist layer is formed directly above the seed layer followed by the formation of a first plurality of openings within the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form first pillar bumps. The first photoresist layer is removed from the semiconductor structure followed by removal of portions of the seed layer extending outward from the first pillar bumps, a portion of the seed layer remains underneath the first pillar bumps.
Bonding wire for semiconductor devices
The present invention has as its object the provision of a bonding wire for semiconductor devices mainly comprised of Ag, in which bonding wire for semiconductor devices, the bond reliability demanded for high density mounting is secured and simultaneously a sufficient, stable bond strength is realized at a ball bond, no neck damage occurs even in a low loop, the leaning characteristic is excellent, and the FAB shape is excellent. To solve this problem, the bonding wire for semiconductor devices according to the present invention contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape.
Bonding wire for semiconductor devices
The present invention has as its object the provision of a bonding wire for semiconductor devices mainly comprised of Ag, in which bonding wire for semiconductor devices, the bond reliability demanded for high density mounting is secured and simultaneously a sufficient, stable bond strength is realized at a ball bond, no neck damage occurs even in a low loop, the leaning characteristic is excellent, and the FAB shape is excellent. To solve this problem, the bonding wire for semiconductor devices according to the present invention contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape.
BONDING WIRE FOR SEMICONDUCTOR DEVICES
Bonding wire for semiconductor devices contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape.
BONDING WIRE FOR SEMICONDUCTOR DEVICES
Bonding wire for semiconductor devices contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape.
Planar integrated circuit package interconnects
Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
Gold-coated silver bonding wire and manufacturing method thereof, and semiconductor device and manufacturing method thereof
A gold-coated silver bonding wire includes: a core material containing silver as a main component; and a coating layer provided on a surface of the core material and containing gold as a main component. The gold-coated silver bonding wire contains gold in a range of not less than 2 mass % nor more than 7 mass %, and at least one sulfur group element selected from the group consisting of sulfur, selenium, and tellurium in a range of not less than 1 mass ppm nor more than 80 mass ppm, with respect to a total content of the bonding wire.