A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.

A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.

A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.

A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.

The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.